公开(公告)号：US20210065828A1

公开(公告)日：2021-03-04

申请号：US16940935

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk YU ,  Bongsoon LIM ,  Yonghyuk CHOI

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20230170031A1

公开(公告)日：2023-06-01

申请号：US18159882

申请日：2023-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Sangwan Nam ,  Jaeduk Yu ,  Yohan Lee

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B41/27

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

公开(公告)号：US20220036953A1

公开(公告)日：2022-02-03

申请号：US17221833

申请日：2021-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin JOE ,  Sangsoo PARK ,  Joonsuc JANG ,  Kihoon KANG ,  Yonghyuk CHOI

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08

Abstract: A nonvolatile memory device that performs two-way channel precharge during programming is provided. A program operation of the nonvolatile memory device simultaneously performs a first precharge operation in a bit line direction and a second precharge operation in a source line direction on channels of a plurality of cell strings before programming a selected memory cell to initialize the channels. The first precharge operation precharges the channels of the plurality of cell strings using a first precharge voltage applied to the bit line through first and second string selection transistors, and the second precharge operation precharges the channels of the plurality of cell strings using a second precharge voltage applied to the source line through first and second ground selection transistors.

公开(公告)号：US20240241649A1

公开(公告)日：2024-07-18

申请号：US18399867

申请日：2023-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk CHOI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A nonvolatile memory device includes a memory block and a control circuit. The memory block includes cell strings. The control circuit controls a first program operation by dividing program data having threshold voltage distributions which have a plurality of states into a plurality of groups, discharging target bit-lines coupled to selected cell strings corresponding to the groups to a ground voltage during a bit-line set-up period of a program loop, discriminating a set-up timing of each of the target bit-lines based on target states of the groups during a first sub period, in which a program voltage and a program pass voltage are ramping and applying the program voltage with a signal pulse having a second target level to a selected word-line, while applying the program pass voltage having a first target level to unselected word-lines, during a second sub period.

公开(公告)号：US20240194268A1

公开(公告)日：2024-06-13

申请号：US18537344

申请日：2023-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk CHOI ,  Seungbum KIM

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/16

Abstract: A memory device is provided. The memory device includes: memory cells respectively connected with word lines; first ground selection transistors connected with a first ground selection line programmed to have a first threshold voltage; second ground selection transistors connected with a second ground selection line programmed to have a second threshold voltage which differs from the first threshold voltage; and a control circuit configured to: control an erase operation to be performed on each of at least one first ground selection transistor of the first ground selection transistors based on a threshold voltage of each of the at least one first ground selection transistor being greater than a predetermined first criterion; and control a threshold voltage of each of the second ground selection transistors to be compared with a predetermined second criterion based on the erase operation on the at least one first ground selection transistor being completed.

公开(公告)号：US20230138604A1

公开(公告)日：2023-05-04

申请号：US17748156

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Yohan LEE ,  Sangwon PARK ,  Jaeduk YU

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C7/10

Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

公开(公告)号：US20220130474A1

公开(公告)日：2022-04-28

申请号：US17334045

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Sangwan NAM ,  Jaeduk YU ,  Yohan LEE

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

公开(公告)号：US20230140959A1

公开(公告)日：2023-05-11

申请号：US18149206

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Bongsoon LIM ,  Hongsoo JEON ,  Jaeduk Yu

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/08 ,  G11C16/04

CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L24/05 ,  H01L24/08 ,  G11C16/08 ,  G11C16/0483 ,  H01L2924/14511 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

公开(公告)号：US20220156014A1

公开(公告)日：2022-05-19

申请号：US17665926

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk YU ,  Bongsoon LIM ,  Yonghyuk CHOI

IPC: G06F3/06

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20210202457A1

公开(公告)日：2021-07-01

申请号：US17026637

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Bongsoon LIM ,  Hongsoo JEON ,  Jaeduk YU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/04 ,  G11C16/08

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.