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公开(公告)号：US20240221844A1
公开(公告)日：2024-07-04
申请号：US18532730
申请日：2023-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk YU , Jonghoon PARK , Yohan LEE , Sangsoo PARK
CPC classification number: G11C16/26 , G11C16/0433 , G11C16/08
Abstract: Provided is an operating method of a nonvolatile memory device. The operating method includes receiving a read command, increasing a voltage applied to a plurality of unselected ground selection lines from an off voltage to an on voltage during a word line setup period, applying a first voltage to a first selected ground selection line corresponding to a first process characteristic, until a first time in the word line setup period, applying a second voltage to the first selected ground selection line after the first time in the word line setup period, applying the first voltage to a second selected ground selection line corresponding to a second process characteristic, until a second time earlier than the first time in the word line setup period, and applying the second voltage to the second selected ground selection line after the second time in the word line setup period.
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2.发明公开公开(公告)号：US20230145467A1
公开(公告)日：2023-05-11
申请号：US18045541
申请日：2022-10-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeduk YU , YOHAN LEE , YONGHYUK CHOI , JIHO CHO
IPC: G11C11/408 , G11C11/4074 , G11C11/4096
CPC classification number: G11C11/4085 , G11C11/4074 , G11C11/4096
Abstract: A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.
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公开(公告)号：US20230138604A1
公开(公告)日：2023-05-04
申请号：US17748156
申请日：2022-05-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk CHOI , Yohan LEE , Sangwon PARK , Jaeduk YU
Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.
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公开(公告)号：US20220130474A1
公开(公告)日：2022-04-28
申请号：US17334045
申请日：2021-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk CHOI , Sangwan NAM , Jaeduk YU , Yohan LEE
Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.
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公开(公告)号：US20240389330A1
公开(公告)日：2024-11-21
申请号：US18444165
申请日：2024-02-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongseok KWON , Jaeduk YU , Bongsoon LIM
Abstract: A semiconductor device is provided. The semiconductor device includes: a first semiconductor structure including a substrate, circuits on the substrate, and a lower interconnection structure electrically connected to the circuits; and a second semiconductor structure including: a plate layer on the first semiconductor structure; gate electrodes and interlayer insulating layers alternately stacked on the plate layer in a first direction that is perpendicular to an upper surface of the plate layer; channel structures passing through the gate electrodes and extending in the first direction; and an upper capacitor structure including an upper gate electrode on the interlayer insulating layers and an upper contact structure extending through the upper gate electrode in the first direction.
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Patent Agency Ranking
公开(公告)号：US20210097010A1
公开(公告)日：2021-04-01
申请号：US16835922
申请日：2020-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinyoung KIM , Jaeduk YU
Abstract: To control initialization of a nonvolatile memory device, before assembling a memory system including a first nonvolatile memory device and a second nonvolatile memory device, information data for initialization of the first nonvolatile memory device are stored in the first nonvolatile memory device. After assembling the memory system, the information data are moved from the first nonvolatile memory device to the second nonvolatile memory device. The first nonvolatile memory device is initialized based on the information data stored in the second nonvolatile memory device. An initialization time of the first nonvolatile memory device is reduced efficiently by moving the information data from the first nonvolatile memory device to the second nonvolatile memory device having the rapid speed of the reading operation and using the information data read from the second nonvolatile memory device.
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公开(公告)号：US20210065828A1
公开(公告)日：2021-03-04
申请号：US16940935
申请日：2020-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk YU , Bongsoon LIM , Yonghyuk CHOI
Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.
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公开(公告)号：US20240290401A1
公开(公告)日：2024-08-29
申请号：US18385185
申请日：2023-10-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yohan LEE , Jaeduk YU , Sangsoo PARK , Yonghyuk CHOI
CPC classification number: G11C16/345 , G11C16/0433 , G11C16/08
Abstract: A method of controlling a nonvolatile memory device, includes: determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells.
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公开(公告)号：US20220075565A1
公开(公告)日：2022-03-10
申请号：US17455037
申请日：2021-11-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk CHOI , Jaeduk YU , Sangwan NAM , Sangwon PARK , Daeseok BYEON , Bongsoon LIM
Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.
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公开(公告)号：US20210064295A1
公开(公告)日：2021-03-04
申请号：US16891457
申请日：2020-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk YU , Bongsoon LIM , Yonghyuk CHOI
IPC: G06F3/06
Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.
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