公开(公告)号：US10586775B2

公开(公告)日：2020-03-10

申请号：US16174934

申请日：2018-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Uk Kim ,  Il-Joon Kim

IPC: H01L23/498 ,  H01L23/66 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H03H7/01 ,  H03H7/38 ,  H03H1/00

Abstract: A memory package includes a multi-level package substrate, a first memory chip, a second memory chip, a first band pass filter and a second band pass filter. The multi-level package substrate includes a plurality of wiring layers and a plurality of insulating layers alternately stacked on one another. The first memory chip is on the multi-level package substrate, and includes a plurality of first memory cells and a first receiver. The second memory chip is on the first memory chip, and includes a plurality of second memory cells and a second receiver. The first band pass filter is in the multi-level package substrate, is connected to the first receiver, and passes a first data signal within a first frequency band. The second band pass filter is in the multi-level package substrate, is connected to the second receiver, and passes a second data signal within the first frequency band.

公开(公告)号：US10055169B2

公开(公告)日：2018-08-21

申请号：US15215072

申请日：2016-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Uk Kim ,  Hanjoon Kim ,  Duckjoo Lee

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0661 ,  G06F3/0673 ,  G06F3/0685 ,  G06F13/1673

Abstract: A memory system includes a plurality of memory devices and a memory controller configured to control the memory devices. The memory controller receives a read request having a variable size, generates at least one memory request having a fixed size in response to the read request, and transmits the at least one memory request to at least one of the memory devices.

公开(公告)号：US09904491B2

公开(公告)日：2018-02-27

申请号：US14956457

申请日：2015-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Uk Kim ,  Jin-Ho Yi

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F3/0679 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F11/1048 ,  G11C2029/0411

Abstract: Provided are a memory device, a memory system, and a method of operating the memory device. A method of operating a memory device including a plurality of random access memory (RAM) chips includes inputting a read command, reading a plurality of pieces of block data including first block data corresponding to the read command from each of the plurality of RAM chips, generating two-dimensional (2D) data by combining the plurality of pieces of block data read from each of the RAM chips, and processing the read command by using the 2D data.