Computing system for transmitting completion early between serially connected electronic devices

    公开(公告)号:US11321254B2

    公开(公告)日:2022-05-03

    申请号:US17007553

    申请日:2020-08-31

    Abstract: A computing system includes a host, a first electronic device including a memory and an accelerator, and a second electronic device including a direct memory access (DMA) engine. Based on a command transmitted from the host through the first electronic device, the DMA engine transmits data and completion information of the command to the first electronic device. The memory includes a data buffer storing the data and a completion queue buffer storing the completion information. The accelerator executes a calculation on the data. The DMA engine transmits the data to the first electronic device and then transmits the completion information to the first electronic device.

    Storage device and storage system performing offloaded tasks from host

    公开(公告)号:US11481125B2

    公开(公告)日:2022-10-25

    申请号:US17019429

    申请日:2020-09-14

    Abstract: A storage device includes a first interface, an operation circuit, and a nonvolatile memory. The first interface receives a first data chunk from a host device. The operation circuit generates first processed data by processing the first data chunk and generates a first signal indicating a size of the first processed data. The nonvolatile memory stores the first processed data in a storage location, when the storage location at which the first processed data are to be stored is designated to the storage device based on the first signal. The first interface outputs the first signal to the host device.

    MEMORY PACKAGES AND RELATED SEMICONDUCTOR PACKAGES

    公开(公告)号:US20190229076A1

    公开(公告)日:2019-07-25

    申请号:US16174934

    申请日:2018-10-30

    Abstract: A memory package includes a multi-level package substrate, a first memory chip, a second memory chip, a first band pass filter and a second band pass filter. The multi-level package substrate includes a plurality of wiring layers and a plurality of insulating layers alternately stacked on one another. The first memory chip is on the multi-level package substrate, and includes a plurality of first memory cells and a first receiver. The second memory chip is on the first memory chip, and includes a plurality of second memory cells and a second receiver. The first band pass filter is in the multi-level package substrate, is connected to the first receiver, and passes a first data signal within a first frequency band. The second band pass filter is in the multi-level package substrate, is connected to the second receiver, and passes a second data signal within the first frequency band.

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