公开(公告)号：US11957071B2

公开(公告)日：2024-04-09

申请号：US17749289

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yukio Hayakawa ,  Jooheon Kang ,  Myunghun Woo ,  Gunwook Yoon ,  Doohee Hwang

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/826 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/841 ,  H10N70/8833

Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.

公开(公告)号：US11778825B2

公开(公告)日：2023-10-03

申请号：US17702967

申请日：2022-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Doohee Hwang

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

公开(公告)号：US11315946B2

公开(公告)日：2022-04-26

申请号：US16838106

申请日：2020-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Doohee Hwang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11524

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.