公开(公告)号：US11264401B2

公开(公告)日：2022-03-01

申请号：US16270570

申请日：2019-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyoung Kim ,  Kwang Soo Kim ,  Seok Cheon Baek ,  Geun Won Lim

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

公开(公告)号：US20210398915A1

公开(公告)日：2021-12-23

申请号：US17462522

申请日：2021-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L23/00 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11133267B2

公开(公告)日：2021-09-28

申请号：US16227919

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L27/11573 ,  H01L23/00 ,  H01L27/11582

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11004860B2

公开(公告)日：2021-05-11

申请号：US16733539

申请日：2020-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Geun Won Lim

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/535 ,  H01L27/11582 ,  H01L21/28

Abstract: A method for fabricating a non-volatile memory device is provided. The method includes forming a channel hole and a first contact hole simultaneously, several times, in order to achieve a desired a high aspect ratio.

公开(公告)号：US10573657B2

公开(公告)日：2020-02-25

申请号：US16206035

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Geun Won Lim

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/535 ,  H01L27/11582 ,  H01L21/28

Abstract: A method for fabricating a non-volatile memory device is provided. The method includes forming a channel hole and a first contact hole simultaneously, several times, in order to achieve a desired a high aspect ratio.