公开(公告)号：US20170294483A1

公开(公告)日：2017-10-12

申请号：US15632969

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masayuki TERAI ,  Gwan-hyeob KOH ,  Dae-hwan KANG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2427 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/17 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L43/08 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.