公开(公告)号：US20230141318A1

公开(公告)日：2023-05-11

申请号：US17879106

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  DONGKYU KIM ,  KYOUNG LIM SUK ,  WONJAE LEE

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L25/0652 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16

Abstract: A redistribution substrate may include a first interconnection layer having a first insulating pattern, a first dummy pattern and a second dummy pattern, the first and second dummy patterns being in the first insulating pattern, and a second interconnection layer stacked on the first interconnection layer, the second interconnection layer having a second insulating pattern, a signal pattern and a power/ground pattern, the signal and power/ground patterns being in the second insulating pattern. The first dummy pattern may be located below the signal pattern, and the second dummy pattern may be located below the power/ground pattern. The first dummy pattern may include dot patterns, and the second dummy pattern may include a plate pattern.

公开(公告)号：US20230101149A1

公开(公告)日：2023-03-30

申请号：US17843967

申请日：2022-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEWON YOO ,  JONGYOUN KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  HYEONJEONG HWANG

IPC: H01L23/367 ,  H01L25/10 ,  H01L23/31 ,  H01L25/18

Abstract: A semiconductor package is disclosed. The semiconductor package may include a first redistribution substrate including a first insulating layer and a first redistribution pattern, a lower semiconductor chip mounted on the first redistribution substrate, a conductive structure disposed on the first redistribution substrate and horizontally spaced apart from the lower semiconductor chip, a first mold layer interposed between the first redistribution substrate and the second redistribution substrate to cover the lower semiconductor chip and the conductive structure, a second redistribution substrate on the first redistribution substrate, the second redistribution substrate including a second insulating layer and a second redistribution pattern, a first heat-dissipation pattern interposed between the lower semiconductor chip and the second insulating layer, and a heat-dissipation pad on the conductive structure. A top surface of the first heat-dissipation pattern may be located at a level higher than a top surface of the conductive structure.