公开(公告)号：US20240312886A1

公开(公告)日：2024-09-19

申请号：US18669118

申请日：2024-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEGWON JANG ,  KYOUNG LIM SUK ,  MINJUN BAE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/16227

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern further includes first fine wire patterns that are less wide than the wire portion of the second redistribution pattern.

公开(公告)号：US20230215799A1

公开(公告)日：2023-07-06

申请号：US18183062

申请日：2023-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  KEUNG BEUM KIM ,  DONGKYU KIM ,  MINJUNG KIM ,  SEOKHYUN LEE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L25/105 ,  H01L23/5386 ,  H01L23/5383 ,  H01L23/49822 ,  H01L21/4857 ,  H01L2924/14361 ,  H01L24/16 ,  H01L24/73 ,  H01L24/17 ,  H01L2924/1431 ,  H01L2224/08225 ,  H01L2924/1433 ,  H01L24/08 ,  H01L2225/1035 ,  H01L2224/16227 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/33 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/1058 ,  H01L2224/33181 ,  H01L2224/73204

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US20210111128A1

公开(公告)日：2021-04-15

申请号：US17130505

申请日：2020-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  Seung-Kwan Ryu ,  Seokhyun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

公开(公告)号：US20240243053A1

公开(公告)日：2024-07-18

申请号：US18457535

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  JOONSUNG KIM ,  SANGJIN BAEK ,  KYOUNG LIM SUK

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/165 ,  H01L2225/06517

Abstract: A semiconductor package includes a first redistribution layer; a first semiconductor chip above the first redistribution layer; a second semiconductor chip above the first semiconductor chip; a second redistribution layer above the second semiconductor chip; a first connection structure on the second redistribution layer; a connection post on the first connection structure; and a connection interconnection layer on the connection post, wherein the connection interconnection layer comprises a connection insulating layer and a connection via extending through the connection insulating layer, and wherein the second redistribution layer and the first redistribution layer are electrically connected to each other through a wire.

公开(公告)号：US20220328389A1

公开(公告)日：2022-10-13

申请号：US17535093

申请日：2021-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.

公开(公告)号：US20220077007A1

公开(公告)日：2022-03-10

申请号：US17235997

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINJUNG KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

公开(公告)号：US20220037294A1

公开(公告)日：2022-02-03

申请号：US17184978

申请日：2021-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONJEONG HWANG ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US20180366411A1

公开(公告)日：2018-12-20

申请号：US16006168

申请日：2018-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYOUNG LIM SUK ,  SEUNG-KWAN RYU ,  SEOKHYUN LEE

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

公开(公告)号：US20240332268A1

公开(公告)日：2024-10-03

申请号：US18739690

申请日：2024-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20240178114A1

公开(公告)日：2024-05-30

申请号：US18227348

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  DONGKYU KIM ,  JI HWANG KIM ,  HYEONJEONG HWANG

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16055 ,  H01L2224/16227 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/351

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.