公开(公告)号：US20230361017A1

公开(公告)日：2023-11-09

申请号：US18119705

申请日：2023-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONJEONG HWANG ,  INHYUNG SONG ,  HYEONSEOK LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/544 ,  H01L21/565 ,  H01L21/486 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/3128 ,  H01L23/3135 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2223/54486 ,  H01L2924/1533 ,  H01L2924/15165

Abstract: Disclosed are packages and their fabrication methods. The package includes: a lower substrate with an upper pad; a lower chip on the lower substrate; a mold layer on the lower chip and the lower substrate; a post extending through the mold layer and provided on the upper pad around the lower chip, the post having a diameter less than a diameter of the upper pad; and an upper substrate on the post and the mold layer, the upper substrate including a lower pad having a diameter greater than the diameter of the post.

公开(公告)号：US20220328389A1

公开(公告)日：2022-10-13

申请号：US17535093

申请日：2021-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.

公开(公告)号：US20220037294A1

公开(公告)日：2022-02-03

申请号：US17184978

申请日：2021-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONJEONG HWANG ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US20240178114A1

公开(公告)日：2024-05-30

申请号：US18227348

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  DONGKYU KIM ,  JI HWANG KIM ,  HYEONJEONG HWANG

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16055 ,  H01L2224/16227 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/351

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.

公开(公告)号：US20220415771A1

公开(公告)日：2022-12-29

申请号：US17670635

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  DONGKYU KIM ,  MINJUNG KIM ,  YEONHO JANG

IPC: H01L23/498 ,  H01L23/31

Abstract: A semiconductor package including a redistribution substrate extending in a first direction and a second direction perpendicular to the first direction, a semiconductor chip mounted on a top surface of the redistribution substrate, and an outer terminal on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, a redistribution insulating layer covering a top surface and a side surface of the under-bump pattern, a protection pattern interposed between the top surface of the under-bump pattern and the redistribution insulating layer, and interposed between the side surface of the under-bump pattern and the redistribution insulating layer, and a redistribution pattern on the under-bump pattern. The outer terminal may be disposed on a bottom surface of the under-bump pattern.

公开(公告)号：US20250132218A1

公开(公告)日：2025-04-24

申请号：US18623488

申请日：2024-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG DON MUN ,  WOOYOUNG KIM ,  YEONHO JANG ,  HYEONJEONG HWANG

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor package includes: a first substrate; a first semiconductor chip; a second semiconductor chip being spaced apart, in a first direction, from the first substrate, the first direction being parallel to a top surface of the first substrate; at least one thermal radiation structure on the first substrate and between the first semiconductor chip and the second semiconductor chip; and a third semiconductor chip on the first semiconductor chip, the second semiconductor chip, and the at least one thermal radiation structure, wherein the at least one thermal radiation structure includes: a thermal radiation post; and a thermal conductive pattern on the thermal radiation post, wherein a bottom surface of the third semiconductor chip is in contact with the thermal conductive pattern, and wherein the top surface of the first substrate is in contact with the thermal radiation post.

公开(公告)号：US20240128145A1

公开(公告)日：2024-04-18

申请号：US18469111

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEONSEOK LEE ,  DONGKYU KIM ,  HYEONJEONG HWANG

IPC: H01L23/367 ,  H01L21/306 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/4878 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3738 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/95 ,  H01L25/0655 ,  H01L25/105 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/95 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15174 ,  H01L2924/3511

Abstract: A semiconductor package includes a redistribution substrate, a sub-package disposed on the redistribution substrate, a semiconductor chip disposed on the redistribution substrate, a heat dissipation structure disposed on the redistribution substrate and surrounding the sub-package and the semiconductor chip, and an encapsulant. The redistribution substrate includes a redistribution structure. The semiconductor chip is positioned side-by-side with the sub-package. The encapsulant encapsulates the sub-package, the semiconductor chip, and the heat dissipation structure.

公开(公告)号：US20250022788A1

公开(公告)日：2025-01-16

申请号：US18666967

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  HYEONJEONG HWANG ,  Sehoon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10

Abstract: An embodiment provides a semiconductor package including: a first redistribution layer structure including a plurality of redistribution vias and a plurality of UBM structures; and a first semiconductor die on the first redistribution layer structure, wherein each of the plurality of UBM structures includes a UBM via; and a UBM wire line extending in a horizontal direction on the UBM via and electrically connecting one of the plurality of redistribution vias and the UBM via in the horizontal direction.

公开(公告)号：US20240243110A1

公开(公告)日：2024-07-18

申请号：US18235643

申请日：2023-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  SUNGEUN JO

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2225/1005 ,  H01L2924/1438 ,  H01L2924/16235

Abstract: Disclosed is a semiconductor package comprising an interposer substrate, a chip stack on the interposer substrate and including first semiconductor chips that are vertically stacked, a second semiconductor chip on the interposer substrate and horizontally spaced apart from the chip stack, a molding layer on the interposer substrate and surrounding the chip stack and the second semiconductor chip, a redistribution layer on the molding layer, and a plurality of conductive posts that vertically penetrate the molding layer and connect the interposer substrate to the redistribution layer.

公开(公告)号：US20240178185A1

公开(公告)日：2024-05-30

申请号：US18357484

申请日：2023-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGKYU KIM ,  KYUNG DON MUN ,  KYOUNG LIM SUK ,  HYEONJEONG HWANG

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/3736 ,  H01L23/5383 ,  H01L23/5384 ,  H10B80/00

Abstract: Disclosed is a semiconductor package comprising a lower circuit part having a first region and a second region horizontally offset from each other and including a connection structure within the first region and a logic chip within the second region, a memory structure that overlaps the connection structure in a vertical direction, and a thermal radiation structure that overlaps the logic chip in the vertical direction. The logic chip and the memory structure are spaced apart in a horizontal direction parallel to a top surface of the logic chip.