公开(公告)号：US20230101149A1

公开(公告)日：2023-03-30

申请号：US17843967

申请日：2022-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEWON YOO ,  JONGYOUN KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  HYEONJEONG HWANG

IPC: H01L23/367 ,  H01L25/10 ,  H01L23/31 ,  H01L25/18

Abstract: A semiconductor package is disclosed. The semiconductor package may include a first redistribution substrate including a first insulating layer and a first redistribution pattern, a lower semiconductor chip mounted on the first redistribution substrate, a conductive structure disposed on the first redistribution substrate and horizontally spaced apart from the lower semiconductor chip, a first mold layer interposed between the first redistribution substrate and the second redistribution substrate to cover the lower semiconductor chip and the conductive structure, a second redistribution substrate on the first redistribution substrate, the second redistribution substrate including a second insulating layer and a second redistribution pattern, a first heat-dissipation pattern interposed between the lower semiconductor chip and the second insulating layer, and a heat-dissipation pad on the conductive structure. A top surface of the first heat-dissipation pattern may be located at a level higher than a top surface of the conductive structure.

公开(公告)号：US20220216190A1

公开(公告)日：2022-07-07

申请号：US17370594

申请日：2021-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  TAEWON YOO ,  MYUNGKEE CHUNG ,  JINCHAN AHN

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip and a redistribution layer. The semiconductor chip includes a semiconductor substrate, a passivation layer, and first power, second power, and signal pads exposed from the passivation layer. The redistribution layer includes a photosensitive dielectric layer, and first to third redistribution patterns and a high-k dielectric pattern that are in the photosensitive dielectric layer. The first, second, and third redistribution patterns are respectively connected to the first power, second power, and signal pads. The high-k dielectric pattern is between the first and second redistribution patterns. The photosensitive dielectric layer includes a first dielectric material. The high-k dielectric pattern includes a second dielectric material whose dielectric constant greater than that of the first dielectric material. The high-k dielectric pattern is in contact with the passivation layer. The passivation layer includes a dielectric material different from the first and second dielectric materials.

公开(公告)号：US20220037295A1

公开(公告)日：2022-02-03

申请号：US17205659

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  TAEWON YOO ,  MYUNGKEE CHUNG

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a bottom package and an upper redistribution layer disposed on the bottom package. The bottom package includes a substrate and a semiconductor chip disposed on the substrate. A conductive pillar extends upwardly from the substrate and is spaced apart from the semiconductor chip. A mold layer is disposed on the substrate and encloses the semiconductor chip and lateral side surfaces of the conductive pillar. The conductive pillar includes a connection pillar configured to electrically connect the substrate to the upper redistribution layer and an alignment pillar that is spaced apart from the connection pillar. The upper redistribution layer includes a redistribution metal pattern configured to be electrically connected to the connection pillar. A first insulating layer is in direct contact with a top surface of the redistribution metal pattern. A top surface of the alignment pillar is in direct contact with the first insulating layer.

公开(公告)号：US20210167007A1

公开(公告)日：2021-06-03

申请号：US16931129

申请日：2020-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  TAEWON YOO ,  MYUNGKEE CHUNG

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L23/00

Abstract: A semiconductor package includes an electrode pad arranged in a first direction parallel to an upper surface of a semiconductor chip, a first protective layer at least partially surrounding an edge of the electrode pad and having a first opening that is above the electrode pad, a second protective layer at least partially surrounding the first protective layer and having a second opening that is above the electrode pad, and a redistribution structure electrically connected to the electrode pad and covering at least a part of an upper surface of the second protective layer. A first width of the first opening in the first direction is equal to or greater than a maximum width of the redistribution structure in the first direction, and a second width of the second opening in the first direction is less than the maximum width of the redistribution structure in the first direction.