公开(公告)号：US11899970B2

公开(公告)日：2024-02-13

申请号：US17742184

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Hee Hyun Nam ,  Younggeon Yoo ,  Jeongho Lee ,  Younho Jeon ,  Ipoom Jeong ,  Chanho Yoon

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0611 ,  G06F3/0622 ,  G06F3/0683

Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.

公开(公告)号：US10671299B2

公开(公告)日：2020-06-02

申请号：US16044024

申请日：2018-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Hyun Nam ,  Youngjin Cho

IPC: G06F3/06

Abstract: The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data.

公开(公告)号：US10403332B2

公开(公告)日：2019-09-03

申请号：US15792973

申请日：2017-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Geun Lee ,  Young Jin Cho ,  Hee Hyun Nam ,  Hyo Deok Shin ,  Young Kwang Yoo

IPC: G11C7/10 ,  G06F12/0879 ,  G06F13/16 ,  G11C8/06 ,  G11C5/04 ,  G11C8/12

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.

公开(公告)号：US10048878B2

公开(公告)日：2018-08-14

申请号：US15132466

申请日：2016-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Hyun Nam ,  Youngjin Cho

IPC: G06F3/06

Abstract: The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data.

公开(公告)号：US09916897B2

公开(公告)日：2018-03-13

申请号：US15055779

申请日：2016-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Hyun Nam ,  Youngjin Cho

IPC: G06F3/06 ,  G11C16/00 ,  G06F11/00

CPC classification number: G11C16/00 ,  G06F11/00

Abstract: A storage device includes nonvolatile memories and a device controller configured to store data being received from an external device in an internal RAM, according to a command and an address being received from the external device. The device controller controls the nonvolatile memories according to the data stored in the internal RAM, distinguishes whether phase bits received with the data and also stored in the internal RAM are valid, and processes the data stored in the internal RAM when the phase bits are valid.