公开(公告)号：US11418361B2

公开(公告)日：2022-08-16

申请号：US16816992

申请日：2020-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boeok Seo ,  Seonbong Kim ,  Hojun Shim

IPC: H04L12/40 ,  H04L45/302 ,  H04L41/5019 ,  H04L67/1097

Abstract: A method of controlling a master device includes, providing a measured service level by measuring a service level with respect to requests of a master device that is connected to a slave device through an interconnect device and generates the request to demand services from the slave device and controlling a power level of a request control circuit included in the master device based on the measured service level. Power consumption of the master device and the system including the master device is reduced without performance degradation by controlling the power level of the request control circuit adaptively based on the measured service level.

公开(公告)号：US10430088B2

公开(公告)日：2019-10-01

申请号：US15821436

申请日：2017-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mina Hwang ,  Kwanggu Lee ,  Hojun Shim

IPC: G06F3/06 ,  G06F13/16

Abstract: A storage device includes a controller that is configured to perform two-way communication with a host. The controller generates a plurality of requests including first requests and second requests associated with the host. The controller orders the plurality of requests such that the plurality of requests include at least one first request and at least two consecutive second requests.

公开(公告)号：US20220283962A1

公开(公告)日：2022-09-08

申请号：US17751798

申请日：2022-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmuk HWANG ,  Jaegeun Park ,  Hojun Shim ,  Byungchul Yoo

IPC: G06F13/16 ,  G06F13/28

Abstract: A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.

公开(公告)号：US11055251B2

公开(公告)日：2021-07-06

申请号：US16853373

申请日：2020-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun Shim

IPC: G06F13/40 ,  G06F3/06

Abstract: A storage device is provided. The storage device includes a field programmable gate array board connected to a first port of the storage device; and a storage controller including a first interface circuit and a second interface circuit. The first interface circuit is connected to the FPGA board, the second interface circuit is connected to a second port of the storage device, at least one port from among the first port and the second port being configured to connect to an external storage device, and the FPGA board is configured to provide a path for transferring data in a peer-to-peer manner between the storage controller and the external storage device without intervention of a host.

公开(公告)号：US09087050B2

公开(公告)日：2015-07-21

申请号：US14088909

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Shim ,  Eunchan Kim

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A memory controller is provided. The memory controller may comprise a first interface configured to provide an interface for communications with a host, and a second interface configured to communicate with the host through the first interface and to provide an interface for communications with a memory. The second interface may include an emulation engine configured to generate a Direct Memory Access (DMA) setup Frame Information Structure (FIS) including ready state information for data communications with the host in response to a command transferred from the host. The second interface may include a storage engine configured to access the host to fetch a physical region descriptor (PRD) before the DMA setup FIS is received from the emulation engine.

Abstract translation: 提供存储器控制器。 存储器控制器可以包括被配置为提供用于与主机通信的接口的第一接口和被配置为通过第一接口与主机通信并且提供用于与存储器通信的接口的第二接口。 第二接口可以包括被配置为响应于从主机传送的命令而生成包括用于与主机进行数据通信的就绪状态信息的直接存储器访问（DMA）建立帧信息结构（FIS）的仿真引擎。 第二接口可以包括被配置为在从仿真引擎接收到DMA建立FIS之前访问主机以获取物理区域描述符（PRD）的存储引擎。