中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

220 records (took 0.05 seconds)

    METHOD AND APPARATUS FOR ENCODING AND DECODING LOW DENSITY PARITY CHECK CODES
    12.
    发明申请
    METHOD AND APPARATUS FOR ENCODING AND DECODING LOW DENSITY PARITY CHECK CODES 审中-公开

    公开(公告)号：US20180026660A1

    公开(公告)日：2018-01-25

    申请号：US15722335

    申请日：2017-10-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hong-sil JEONG ,  Se-ho MYUNG ,  Kyung-joong KIM

    IPC: H03M13/11 ,  H03M13/25

    CPC classification number: H03M13/1165 ,  H03M13/1185 ,  H03M13/255

    Abstract: A transmitting apparatus includes: a low density parity check (LDPC) encoder configured to encode information bits to generate parity bits based on a parity check matrix according to a code rate of 8/15 and a code length of 64800; an interleaver configured to interleave an LDPC codeword including the information bits and parity bits; and a mapper configured to map the interleaved LDPC codeword onto constellation points, wherein the parity check matrix comprises an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is defined by a specific table indicating indices of rows at which a value “1” is positioned in a 0-th column of an i-th column group in the parity check matrix.

    TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF
    18.
    发明申请
    TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF 审中-公开
    发送装置及其交换方法

    公开(公告)号：US20160344418A1

    公开(公告)日：2016-11-24

    申请号：US14715908

    申请日：2015-05-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Se-ho MYUNG ,  Hong-sil JEONG ,  Kyung-joong KIM

    IPC: H03M13/27 ,  H04L1/00 ,  H03M13/11

    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

    Abstract translation: 提供发送装置。 发送装置包括：编码器，被配置为基于奇偶校验矩阵通过LDPC编码生成低密度奇偶校验（LDPC）码字; 配置为交织所述LDPC码字的交织器; 以及调制器，被配置为将交织的LDPC码字映射到调制符号，其中所述调制器还被配置为将构成所述LDPC码字的多个比特组中的预定比特组中包括的比特映射到所述调制符号的预定比特 。

    TRANSMITTER AND SHORTENING METHOD THEREOF
    20.
    发明申请
    TRANSMITTER AND SHORTENING METHOD THEREOF 审中-公开
    发射机及其发射方法

    公开(公告)号：US20160261374A1

    公开(公告)日：2016-09-08

    申请号：US15130181

    申请日：2016-04-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Joong KIM ,  Se-ho MYUNG ,  Hong-sil JEONG

    IPC: H04L1/00 ,  H03M13/11 ,  G06F11/10

    CPC classification number: H03M13/1157 ,  G06F11/1004 ,  H03M13/1148 ,  H03M13/1165 ,  H03M13/1191 ,  H03M13/152 ,  H03M13/253 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/611 ,  H03M13/618 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0063 ,  H04L1/0069

    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

    Abstract translation: 提供发射机。 发射机包括：外部编码器，被配置为对输入比特进行编码以产生包括输入比特和奇偶校验比特的外部编码比特; 零填充器，被配置为构成包括外部编码比特和零比特的低密度奇偶校验（LDPC）信息比特; 以及LDPC编码器，被配置为对所述LDPC信息比特进行编码，其中所述LDPC信息比特被分成多个比特组，并且其中所述零填充器将零比特填充到所述多个比特组中的至少一些比特组， 以相同数量的比特来构成基于预定缩短模式的LDPC信息比特，该缩短模式规定多个比特组中的一些比特组不被顺序地置于LDPC信息比特中。

Patent Agency Ranking