公开(公告)号：US11056193B2

公开(公告)日：2021-07-06

申请号：US16442672

申请日：2019-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Won Yun ,  Jin-Young Kim ,  Il-Han Park ,  Hyun Seo ,  Bong-Soon Lim

IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11582 ,  G11C11/56

Abstract: A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.

公开(公告)号：US12230328B2

公开(公告)日：2025-02-18

申请号：US17868900

申请日：2022-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Seo

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a cell area including a plurality of word lines stacked on a substrate, at least one ground select line between the plurality of word lines and substrate, and a plurality of channel structures passing through the plurality of word lines and the at least one ground select line, and a peripheral circuit area including peripheral circuits controlling the cell area. The peripheral circuits input a first ground select bias voltage to the at least one ground select line during a first program time to a program word line selected from among the plurality of word lines, and input a second ground select bias voltage having a magnitude different from the first ground select bias voltage to the at least one ground select line during a second program time, the second program voltage different from the first program voltage.

公开(公告)号：US12181953B2

公开(公告)日：2024-12-31

申请号：US18374717

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wandong Kim ,  Jinyoung Kim ,  Sehwan Park ,  Hyun Seo ,  Sangwan Nam

IPC: G11C7/00 ,  G06F11/07 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

公开(公告)号：US20230044730A1

公开(公告)日：2023-02-09

申请号：US17968912

申请日：2022-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wandong KIM ,  Jinyoung KIM ,  Sehwan PARK ,  Hyun Seo ,  Sangwan NAM

IPC: G06F11/07 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.