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    Nonvolatile memory device, vertical NAND flash memory device and SSD device including the same
    1.
    发明授权
    Nonvolatile memory device, vertical NAND flash memory device and SSD device including the same 有权

    公开(公告)号：US10804293B2

    公开(公告)日：2020-10-13

    申请号：US16440299

    申请日：2019-06-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Won Park ,  Sang-Wan Nam ,  Bong-Soon Lim

    IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11573 ,  G06F3/06 ,  H01L27/1157 ,  H01L27/11565

    Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.

    Non-volatile memory
    3.
    发明授权
    Non-volatile memory 有权

    公开(公告)号：US11296066B2

    公开(公告)日：2022-04-05

    申请号：US16937815

    申请日：2020-07-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Hwa Yun ,  Pan-Suk Kwak ,  Chan-Ho Kim ,  Bong-Soon Lim

    IPC: G11C16/04 ,  H01L25/18 ,  G11C16/08 ,  G11C16/24 ,  G11C13/00 ,  H01L25/065 ,  H01L23/00

    Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

    Non-volatile memory
    4.
    发明授权
    Non-volatile memory 有权

    公开(公告)号：US11075216B2

    公开(公告)日：2021-07-27

    申请号：US16449286

    申请日：2019-06-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Hwa Yun ,  Pan-Suk Kwak ,  Chan-Ho Kim ,  Bong-Soon Lim

    IPC: G11C11/00 ,  H01L27/11573 ,  G11C16/08 ,  H01L27/24 ,  G11C16/04 ,  G11C13/00 ,  H01L45/00 ,  G11C11/56 ,  H01L27/11582 ,  G11C7/04 ,  G11C5/02 ,  G11C5/06

    Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

    Nonvolatile memory device
    6.
    发明授权
    Nonvolatile memory device 有权

    公开(公告)号：US10170192B2

    公开(公告)日：2019-01-01

    申请号：US15717992

    申请日：2017-09-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： June-Hong Park ,  Ki-Whan Song ,  Bong-Soon Lim ,  Su-Chang Jeon ,  Jin-Young Kim ,  Chang-Yeon Yu ,  Dong-Kyo Shim ,  Seong-Jin Kim

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

    Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.

    Nonvolatile memory device with capability of determing degradation of data erase characteristics
    8.
    发明授权
    Nonvolatile memory device with capability of determing degradation of data erase characteristics 有权

    公开(公告)号：US11289170B2

    公开(公告)日：2022-03-29

    申请号：US17021407

    申请日：2020-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong-Jin Song ,  Hyun-Wook Park ,  Bong-Soon Lim ,  Do-Bin Kim

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

    Non-volatile memory devices having enhanced erase control circuits therein
    9.
    发明授权
    Non-volatile memory devices having enhanced erase control circuits therein 有权

    公开(公告)号：US11056193B2

    公开(公告)日：2021-07-06

    申请号：US16442672

    申请日：2019-06-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Se-Won Yun ,  Jin-Young Kim ,  Il-Han Park ,  Hyun Seo ,  Bong-Soon Lim

    IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11582 ,  G11C11/56

    Abstract: A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.

    Memory device, memory system, and power management method
    10.
    发明授权
    Memory device, memory system, and power management method 有权
    存储器件，存储器系统和电源管理方法

    公开(公告)号：US08929170B2

    公开(公告)日：2015-01-06

    申请号：US13773125

    申请日：2013-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Soo Park ,  Bong-Soon Lim ,  Hyuk-Jun Yoo

    IPC: G11C5/14 ,  G11C8/04 ,  G11C8/06 ,  G11C7/22

    CPC classification number: G11C5/14 ,  G11C5/144 ,  G11C5/148 ,  G11C7/22 ,  G11C8/04 ,  G11C8/06

    Abstract: A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation, and delaying execution of second high power operation through a first waiting period that ends upon completion of the first high power operation, while applying a reference voltage to a second word line of the second memory die indicated by the second address.

    Abstract translation: 一种电源管理方法，包括：在接收到所述第一命令之后，接收到具有指示在第一存储器管芯中立即执行的第一高功率操作的第一地址的第一命令，接收到具有指示第二高功率操作的第二地址的第二命令， 使得第二高功率操作的立即执行将与第一高功率操作重叠，并且通过在第一高功率操作完成时结束的第一等待时段来延迟第二高功率操作的执行，同时将参考电压施加到 由第二地址指示的第二存储器管芯的第二字线。

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