-
公开(公告)号：US09299445B2
公开(公告)日：2016-03-29
申请号：US14746716
申请日：2015-06-22
发明人： Il-Han Park , Go-Eun Jung
CPC分类号： G11C16/10 , G11C7/10 , G11C16/0483 , G11C16/08 , G11C16/3427
摘要： A method of operating a nonvolatile memory device may include applying a first voltage greater than a ground voltage to a selected word line during a first time period; applying a second voltage to an unselected word line during a second time period that is later than the first time period; and applying a third voltage greater than the first voltage and the second voltage to the selected word line during the second time period. The second time period includes a third time period during which a voltage level of the unselected word line increases to the second voltage from a fourth voltage that is less than the second voltage, and during which a voltage level of the selected word line increases to the third voltage from the first voltage.
摘要翻译： 操作非易失性存储器件的方法可以包括在第一时间段期间将大于接地电压的第一电压施加到所选择的字线; 在比第一时间段晚的第二时间段期间将第二电压施加到未选择的字线; 以及在所述第二时间段期间将大于所述第一电压和所述第二电压的第三电压施加到所选择的字线。 第二时间段包括第三时间段，在该第三时间段期间，未选择字线的电压电平从小于第二电压的第四电压增加到第二电压，并且在此期间，所选字线的电压电平增加到 第一电压的第三电压。
-
公开(公告)号：US10892015B2
公开(公告)日：2021-01-12
申请号：US16822905
申请日：2020-03-18
发明人： Kang-Bin Lee , Il-Han Park , Jong-Hoo Jo
IPC分类号： G11C16/10 , G11C16/04 , G11C16/26 , G11C16/34 , G11C16/08 , H01L27/11556 , H01L27/11582
摘要： In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.
-
公开(公告)号：US10748617B2
公开(公告)日：2020-08-18
申请号：US16222038
申请日：2018-12-17
发明人： Kui-Han Ko , Jin-Young Kim , Il-Han Park , Bong-Soon Lim
IPC分类号： G11C8/10 , G11C16/04 , G11C11/56 , G11C16/26 , G11C16/08 , G11C16/10 , H01L27/11582 , H01L27/11556
摘要： A method of operating a nonvolatile memory device is provided where the nonvolatile memory device includes a plurality of cell strings, and each cell string includes a plurality of multi-level cells. a voltage of a selected word line is sequentially changed to sequentially have a plurality of read voltages for determining threshold voltage states of the plurality of multi-level cells. A voltage of an adjacent word line adjacent to the selected word line is sequentially changed in synchronization with voltage changing time points of the selected word line. A load of the selected word line is reduced and an operation speed of the nonvolatile memory device is increased by synchronizing the voltage change of the selected word line and the voltage change of the adjacent word line in the same direction.
-
公开(公告)号：US09406383B2
公开(公告)日：2016-08-02
申请号：US14606284
申请日：2015-01-27
发明人： Il-Han Park , Su-Yong Kim
CPC分类号： G11C16/08 , G11C11/5628 , G11C16/12
摘要： A non-volatile memory device includes a first word line, a second word line, first memory cells, second memory cells, and an address decoder. The second word line is adjacent to the first word line. The first memory cells are connected to the first word line. The second memory cells are connected to the second word line. The second memory cells are connected to the first memory cells, respectively. The address decoder applies a first voltage to the first word line and applies a second voltage to the second word line in an over program period of the first memory cells. The first voltage is higher than a program voltage of the first and second memory cells. The second voltage is lower than a pass voltage of the first and second memory cells.
摘要翻译： 非易失性存储器件包括第一字线，第二字线，第一存储器单元，第二存储器单元和地址解码器。 第二个字线与第一个字线相邻。 第一个存储单元连接到第一个字线。 第二存储单元连接到第二字线。 第二存储单元分别连接到第一存储单元。 地址解码器向第一字线施加第一电压，并在第一存储器单元的过程编程周期中向第二字线施加第二电压。 第一电压高于第一和第二存储器单元的编程电压。 第二电压低于第一和第二存储单元的通过电压。
-
5.发明授权Page buffer, memory device comprising page buffer, and related method of operation 有权页面缓冲器，包括页面缓冲器的存储器件以及相关的操作方法公开(公告)号：US09007850B2
公开(公告)日：2015-04-14
申请号：US13718105
申请日：2012-12-18
发明人： Sang-Hyun Joo , Il-Han Park , Ki-Hwan Song
CPC分类号： G11C11/24 , G11C16/02 , G11C16/10 , G11C2216/14
摘要： A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.
摘要翻译： 页面缓冲器包括被配置为存储从外部设备接收的数据的静态锁存器和配置成通过浮动节点接收存储在静态锁存器中的数据的动态锁存器，该动态锁存器包括存储电容器，写入晶体管被配置为写入 浮动节点到存储电容器的数据，以及被配置为读取存储电容器的数据的读取晶体管，以及共享浮动节点的写入晶体管和读取晶体管。
-
6.发明授权Semiconductor memory device for and method of applying temperature-compensated word line voltage during read operation 有权用于在读取操作期间施加温度补偿字线电压的半导体存储器件和方法公开(公告)号：US09001579B2
公开(公告)日：2015-04-07
申请号：US14058508
申请日：2013-10-21
发明人： Young-Sun Song , Eung-Suk Lee , Il-Han Park
CPC分类号： G11C16/08 , G11C7/04 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26
摘要： A semiconductor memory device configured to apply a temperature-compensated word line voltage to a word line during a data read operation includes a memory cell array including a plurality of word lines, a plurality of non-volatile memory cells connected to the word lines, and a word line voltage application unit configured to apply a temperature-compensated read voltage to a selected word line and to apply a temperature-compensated pass voltage to at least one unselected word line during a read operation.
摘要翻译： 被配置为在数据读取操作期间将温度补偿字线电压施加到字线的半导体存储器件包括包括多个字线的存储单元阵列，连接到字线的多个非易失性存储器单元，以及 字线电压施加单元，被配置为将温度补偿读取电压施加到所选择的字线，并且在读取操作期间将温度补偿的通过电压施加到至少一个未选择的字线。
-
公开(公告)号：US11238942B2
公开(公告)日：2022-02-01
申请号：US17023556
申请日：2020-09-17
发明人： Seung-Bum Kim , Il-Han Park , Ji-Young Lee , Su-Chang Jeon
摘要： Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.
-
公开(公告)号：US11056193B2
公开(公告)日：2021-07-06
申请号：US16442672
申请日：2019-06-17
发明人： Se-Won Yun , Jin-Young Kim , Il-Han Park , Hyun Seo , Bong-Soon Lim
IPC分类号： G11C16/16 , G11C16/04 , H01L27/11582 , G11C11/56
摘要： A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.
-
公开(公告)号：US10937508B2
公开(公告)日：2021-03-02
申请号：US16364588
申请日：2019-03-26
发明人： Seung-Bum Kim , Il-Han Park , Ji-Young Lee , Su-Chang Jeon
IPC分类号： G11C16/26 , G11C11/56 , G11C16/24 , G11C16/10 , G11C16/34 , G06F11/10 , G11C29/52 , G11C16/14 , G11C16/04
摘要： Nonvolatile memory device includes a memory cell array including pages, each of the pages including memory cells storing data bits, each of the data bits being selectable by a different threshold voltage, a page buffer circuit coupled to the memory cell array through bit-lines, the page buffer circuit including page buffers to sense data from selected memory cells, and perform a first read operation and a second read operation, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch configured to sequentially store results of the two sequential sensing operations, and a control circuit to control the page buffers to store a result of the first read operation, reset the latches after completion of the first read operation, and perform the second read operation based on a valley determined based on the result of the first read operation.
-
公开(公告)号：US09087590B2
公开(公告)日：2015-07-21
申请号：US13970462
申请日：2013-08-19
发明人： Il-Han Park , Go-Eun Jung
CPC分类号： G11C16/10 , G11C7/10 , G11C16/0483 , G11C16/08 , G11C16/3427
摘要： A nonvolatile memory device and a method of programming the nonvolatile semiconductor memory device are disclosed. The programming method includes applying a first voltage greater than a ground voltage to a selected word line at a first time; applying a second voltage greater than the first voltage to the selected word line at a second time that occurs after a predetermined period from the first time; applying the ground voltage to a first unselected word line directly adjacent to the selected word line at the first time; and applying a third voltage greater than the ground voltage to the first unselected word line at the second time.
摘要翻译： 公开了非易失性存储器件和非易失性半导体存储器件的编程方法。 编程方法包括：在第一时间向所选字线施加大于接地电压的第一电压; 在从第一次开始的预定时段之后的第二时间向所选择的字线施加大于第一电压的第二电压; 在第一次将接地电压施加到与所选字线直接相邻的第一未选字线; 以及在所述第二时间将大于所述接地电压的第三电压施加到所述第一未选择字线。
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.018 秒)
