公开(公告)号：US10038428B2

公开(公告)日：2018-07-31

申请号：US15254272

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K3/35 ,  H03K3/356 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  H03K19/20 ,  G11C7/10

CPC classification number: H03K3/356121 ,  G11C7/1006 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  H03K19/20

Abstract: In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

公开(公告)号：US12126343B2

公开(公告)日：2024-10-22

申请号：US17983929

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwoo Kim ,  Minsu Kim ,  Yonggeol Kim ,  Hyun Lee ,  Hyunchul Hwang

IPC: H03K3/037 ,  H03K3/356 ,  H03K3/3562 ,  H03K19/00

CPC classification number: H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/3562 ,  H03K19/0002

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

公开(公告)号：US11575366B2

公开(公告)日：2023-02-07

申请号：US17583257

申请日：2022-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang

IPC: H03K3/037 ,  H03K3/356 ,  H03K3/012 ,  G01R31/3185 ,  G01R31/317 ,  H03K19/20

Abstract: A low power flip-flop includes first to fourth signal generation circuits and an inverter. The first signal generation circuit receives the clock signal, the data input signal, and a first internal signal that is an output of the second signal generation circuit and generates a second internal signal. The inverter receives the first internal signal and generates an inverted first internal signal. The second signal generation circuit receives the first internal signal and the output signal that is an output of the third signal generation circuit, and generates the inverted output signal. The third signal generation circuit receives the clock signal and the inverted output signal and generates the output signal. The fourth signal generation circuit receives the inverted first internal signal, the second internal signal, and the clock signal and generates the first internal signal.

公开(公告)号：US11545964B2

公开(公告)日：2023-01-03

申请号：US17025511

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyun Choi ,  Hyunchul Hwang ,  Minsu Kim

IPC: H03K3/037 ,  G01R31/3185 ,  G01R31/3177 ,  G06F1/10 ,  H03K3/356

Abstract: High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.