公开(公告)号：US20150358024A1

公开(公告)日：2015-12-10

申请号：US14716106

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin KIM ,  Chang Hoon Baek ,  Sang Kyu Lee ,  Jae Youl Lee

IPC: H03L7/08 ,  H03L7/187 ,  H03L7/091 ,  H03L7/099 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/0807 ,  H03L1/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/187 ,  H03L2207/06 ,  H03L2207/50

Abstract: A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.

Abstract translation: 一种时钟数据恢复电路，包括：数字相位检测器和解串器，被配置为使用恢复时钟信号对串行数据进行采样，以产生对应于串行数据和恢复时钟之间的相位差的上相位误差信号和下行相位误差信号 信号; 数字环路滤波器，其被配置为基于对所述上下相位误差信号进行计数的结果来生成上位编码和下精细码; 配置为通过使用上下相位误差信号和上下精细码产生上调微调码和下调微调码的环路组合器; 以及数字控制振荡器，被配置为产生具有随着上下微调代码而改变的频率的恢复时钟信号。