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公开(公告)号：US11709629B2
公开(公告)日：2023-07-25
申请号：US17455037
申请日：2021-11-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jaeduk Yu , Sangwan Nam , Sangwon Park , Daeseok Byeon , Bongsoon Lim
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C16/24 , H10B41/27 , H10B43/27
Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.
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公开(公告)号：US11183250B2
公开(公告)日：2021-11-23
申请号：US16661351
申请日：2019-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk Yu , Dongkyo Shim
Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. when the When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.
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公开(公告)号：US20210149598A1
公开(公告)日：2021-05-20
申请号：US16918310
申请日：2020-07-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jaeduk Yu , Sangwan Nam , Sangwon Park , Daeseok Byeon , Bongsoon Lim
Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.
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公开(公告)号：US12224277B2
公开(公告)日：2025-02-11
申请号：US18149206
申请日：2023-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Bongsoon Lim , Hongsoo Jeon , Jaeduk Yu
IPC: H01L23/528 , G11C16/04 , G11C16/08 , H01L23/00 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/112
Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.
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公开(公告)号：US11829645B2
公开(公告)日：2023-11-28
申请号：US17665926
申请日：2022-02-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk Yu , Bongsoon Lim , Yonghyuk Choi
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0652 , G06F3/0653 , G06F3/0679
Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.
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Patent Agency Ranking
16.发明公开公开(公告)号：US20230146041A1
公开(公告)日：2023-05-11
申请号：US18052428
申请日：2022-11-03
Applicant: Samsung Electronics Co., Ltd.
IPC: G06F3/06
CPC classification number: G06F3/0607 , G06F3/064 , G06F3/0679 , G06F3/0653
Abstract: According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.
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公开(公告)号：US11581297B2
公开(公告)日：2023-02-14
申请号：US17026637
申请日：2020-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Bongsoon Lim , Hongsoo Jeon , Jaeduk Yu
IPC: H01L23/528 , H01L23/522 , H01L25/18 , H01L25/065 , H01L23/00 , G11C16/08 , G11C16/04
Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.
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公开(公告)号：US11380405B2
公开(公告)日：2022-07-05
申请号：US16810559
申请日：2020-03-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeduk Yu , Jinyoung Kim
Abstract: A storage device includes a first memory device including a plurality of memory blocks, and a plurality of pages included in each of the plurality of memory blocks, a second memory device configured to store first degradation information of the first memory device, and a controller configured to perform a first read operation on the first memory device using a first read voltage, to acquire the first degradation information, and to perform a second read operation on the first memory device using a second read voltage. The second read voltage is calculated using second degradation information of the first memory device estimated using the first degradation information. Each of the first degradation information and the second degradation information includes the number of error bits of each of the plurality of pages.
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公开(公告)号：US11275528B2
公开(公告)日：2022-03-15
申请号：US16891457
申请日：2020-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk Yu , Bongsoon Lim , Yonghyuk Choi
IPC: G06F3/06
Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.
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公开(公告)号：US20220059172A1
公开(公告)日：2022-02-24
申请号：US17520276
申请日：2021-11-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeduk Yu , Dongkyo Shim
Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. when the When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.
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