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    Nonvolatile memory device
    2.
    发明授权
    Nonvolatile memory device 有权

    公开(公告)号：US11200002B2

    公开(公告)日：2021-12-14

    申请号：US16918310

    申请日：2020-07-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

    IPC: G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    3.
    发明公开
    MEMORY DEVICE AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240194274A1

    公开(公告)日：2024-06-13

    申请号：US18531872

    申请日：2023-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Yohan Lee

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/28

    CPC classification number: G11C16/3404 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/28

    Abstract: A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.

    NONVOLATILE MEMORY DEVICE HAVING CELL-OVER-PERIPHERY (COP) STRUCTURE WITH ADDRESS RE-MAPPING
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING CELL-OVER-PERIPHERY (COP) STRUCTURE WITH ADDRESS RE-MAPPING 有权

    公开(公告)号：US20230013747A1

    公开(公告)日：2023-01-19

    申请号：US17935502

    申请日：2022-09-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

    IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08

    Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

    Three-dimensional semiconductor memory device
    5.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11515325B2

    公开(公告)日：2022-11-29

    申请号：US17025479

    申请日：2020-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bongsoon Lim ,  Sang-Wan Nam ,  Sang-Won Park ,  Sang-Won Shim ,  Hongsoo Jeon ,  Yonghyuk Choi

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  G11C7/18 ,  H01L27/11556 ,  H01L27/11526 ,  G11C8/14 ,  H01L27/11519

    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

    Nonvolatile memory device with address re-mapping
    6.
    发明授权
    Nonvolatile memory device with address re-mapping 有权

    公开(公告)号：US11501847B2

    公开(公告)日：2022-11-15

    申请号：US17022967

    申请日：2020-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

    IPC: G11C16/10 ,  G11C29/00 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10 ,  G11C29/12

    Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

    Nonvolatile memory device having cell-over-periphery (COP) structure with address re-mapping
    7.
    发明授权
    Nonvolatile memory device having cell-over-periphery (COP) structure with address re-mapping 有权

    公开(公告)号：US11467932B2

    公开(公告)日：2022-10-11

    申请号：US16865948

    申请日：2020-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

    IPC: G11C16/10 ,  G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

    Nonvolatile memory device performing two-way channel precharge
    10.
    发明授权
    Nonvolatile memory device performing two-way channel precharge 有权

    公开(公告)号：US11450386B2

    公开(公告)日：2022-09-20

    申请号：US17221833

    申请日：2021-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungmin Joe ,  Sangsoo Park ,  Joonsuc Jang ,  Kihoon Kang ,  Yonghyuk Choi

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

    Abstract: A nonvolatile memory device that performs two-way channel precharge during programming is provided. A program operation of the nonvolatile memory device simultaneously performs a first precharge operation in a bit line direction and a second precharge operation in a source line direction on channels of a plurality of cell strings before programming a selected memory cell to initialize the channels. The first precharge operation precharges the channels of the plurality of cell strings using a first precharge voltage applied to the bit line through first and second string selection transistors, and the second precharge operation precharges the channels of the plurality of cell strings using a second precharge voltage applied to the source line through first and second ground selection transistors.

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