公开(公告)号：US20230076184A1

公开(公告)日：2023-03-09

申请号：US17875949

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Bo SHIM ,  Sung Bum KIM ,  Ji Hwang KIM

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31

Abstract: A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.

公开(公告)号：US20210343617A1

公开(公告)日：2021-11-04

申请号：US17376570

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Jong Bo SHIM ,  Jang Woo LEE ,  Yung Cheol KONG ,  Young Hoon HYUN

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

公开(公告)号：US20160093541A1

公开(公告)日：2016-03-31

申请号：US14714667

申请日：2015-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungduk BAEK ,  Ji Hwang KIM ,  Taeje CHO

IPC: H01L21/66 ,  H01L23/525 ,  H01L21/768 ,  G01R31/26

CPC classification number: H01L22/14 ,  G01R31/2601 ,  H01L22/32 ,  H01L23/5256 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern.

Abstract translation: 制造半导体封装的方法包括提供包括电路图案的半导体芯片，连接焊盘，第一测试焊盘和第二测试焊盘，每个连接焊盘，第一测试焊盘和第二测试焊盘分别电连接到 所述电路图案，通过向所述第一测试焊盘施加第一测试电压和对所述第二测试焊盘施加第二测试电压来评估所述半导体芯片的电特性，所述第二测试电压高于所述第一测试电压，并且电连接所述第二测试电压 测试板从电路图案。