公开(公告)号：US20240055398A1

公开(公告)日：2024-02-15

申请号：US18309250

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong Bin Yim ,  Ji-Yong Park ,  Jin-Woo Park ,  Jong Bo Shim

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H10B80/00 ,  H01L23/3107 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32137 ,  H01L2224/32245 ,  H01L2224/32225 ,  H01L2224/33051 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2924/1431 ,  H01L2924/1443 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441

Abstract: A semiconductor package includes a first substrate, a memory semiconductor package on a first surface of the first substrate, an adhesive layer between the first surface of the first substrate and the memory semiconductor package, a wire extending from an upper surface of the memory semiconductor package and connected to the first substrate, a logic semiconductor chip on the first surface of the first substrate, a first connection terminal between the first surface of the first substrate and the logic semiconductor chip, and a molding layer, wherein a first height of the memory semiconductor package is smaller than a second height of the logic semiconductor chip, and wherein an uppermost surface of the molding layer and the upper surface of the logic semiconductor chip are coplanar.