公开(公告)号：US20160012880A1

公开(公告)日：2016-01-14

申请号：US14858140

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yun KIM ,  Jong-Pil SON ,  Su-A KIM ,  Chul-Woo PARK ,  Hong-Sun HWANG

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/408 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract translation: 操作易失性存储器件的方法包括存储弱单元行的地址信息。 根据一些示例，在写入弱单元行之后，在预定时间内对弱单元行执行刷新操作。 根据一些示例，可以以对正常单元行的写恢复时间更长的写恢复时间来执行对弱单元行的写入操作。

公开(公告)号：US20140241098A1

公开(公告)日：2014-08-28

申请号：US14069188

申请日：2013-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Young-Soo SOHN ,  Chul-Woo PARK ,  Cheol-Heui PARK

IPC: G11C8/06

CPC classification number: G11C8/06 ,  G11C7/12 ,  G11C8/10 ,  G11C16/24 ,  G11C29/18 ,  G11C2029/1204 ,  G11C2029/1806

Abstract: A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.

Abstract translation: 可以提供一种存储器件，其包括包括多个子阵列的存储单元阵列，每个子阵列具有连接到位线的多个存储器单元; 配置为接收行地址和列地址的地址缓冲器; 以及列解码器，被配置为从地址缓冲器接收列地址，并且对于每个子阵列，基于应用的不同偏移值从多个列选择线中选择与列地址相对应的列选择线 分别到子阵列。 所选择的列选择线分别对应于具有不同物理位置的位线，根据不同的偏移值。

公开(公告)号：US20140140153A1

公开(公告)日：2014-05-22

申请号：US13804690

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil SON ,  Jae-Sung KIM ,  Uk-Song KANG ,  Young-Soo SOHN

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C29/806 ,  G11C29/808 ,  G11C2029/4402

Abstract: A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not.

Abstract translation: 控制半导体存储器件的修复操作的修复控制电路包括行匹配块和列匹配块。 行匹配块存储指示多个行组中的一个或多个故障行组的故障组信息。 通过对与多个字线对应的多个行地址进行分组来确定行组。 行匹配块基于输入行地址和故障组信息生成组匹配信号，使得组匹配信号指示包括输入行地址的故障行组。 列匹配块存储故障存储器单元的故障列地址，并且基于输入列地址，组匹配信号和故障列地址生成修复控制信号，使得修复控制信号指示是否执行修复操作或 不。