公开(公告)号：US20140149652A1

公开(公告)日：2014-05-29

申请号：US14090510

申请日：2013-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Woo PARK ,  Dong-Soo KANG ,  Su-A KIM ,  Jun-hee YOO ,  Hak-Soo YU ,  Jae-Youn YOUN ,  Sung-hyun LEE ,  Kyoung-Heon JEONG ,  Hyo-Jin CHOI ,  Young-Soo SOHN

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F12/0223 ,  G06F12/0292 ,  G11C29/76 ,  G11C29/84

Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Abstract translation: 在一个示例性实施例中，存储器系统包括存储器模块和存储器控制器。 配置存储器模块基于存储器模块的不良页面的数量生成存储器模块的密度信息，坏页面是具有故障的页面。 存储器控制器被配置为基于从存储器模块接收的密度信息将连续的物理地址映射到存储器模块的动态随机存取存储器（显存）地址。

公开(公告)号：US20140355332A1

公开(公告)日：2014-12-04

申请号：US14219374

申请日：2014-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youn YOUN ,  Su-A KIM ,  Chul-Woo PARK ,  Young-Soo SOHN

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C7/02 ,  G11C7/1063 ,  G11C11/40611 ,  G11C11/40618

Abstract: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.

Abstract translation: 提供了一种易失性存储器件的刷新方法。 该方法包括：随着对第一存储器区域的访问次数的增加，检测影响第二存储器区域的多个干扰; 当检测到的干扰次数达到参考值时，将来自易失性存储器件的警报信号输出到易失性存储器件的外部; 以及响应于所述警报信号对所述第二存储区域执行刷新操作。

公开(公告)号：US20180174959A1

公开(公告)日：2018-06-21

申请号：US15677054

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ju KIM ,  Su-A KIM ,  Soo-Young KIM ,  Min-Woo WON ,  Bok-Yeon WON ,  Ji-Suk KWON ,  Young-Ho KIM ,  Ji-Hak YU ,  Hyun-Chul YOON ,  Seok-Jae LEE ,  Sang-Keun HAN ,  Woong-Dai KANG ,  Hyuk-Joon KWON ,  Bum-Jae LEE

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/552 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5225 ,  G11C7/06 ,  G11C7/1057 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4097 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/06 ,  H01L24/20 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/06155 ,  H01L2224/06159 ,  H01L2224/12105 ,  H01L2924/18162 ,  H01L2924/3025

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

公开(公告)号：US20160012880A1

公开(公告)日：2016-01-14

申请号：US14858140

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yun KIM ,  Jong-Pil SON ,  Su-A KIM ,  Chul-Woo PARK ,  Hong-Sun HWANG

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/408 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract translation: 操作易失性存储器件的方法包括存储弱单元行的地址信息。 根据一些示例，在写入弱单元行之后，在预定时间内对弱单元行执行刷新操作。 根据一些示例，可以以对正常单元行的写恢复时间更长的写恢复时间来执行对弱单元行的写入操作。

公开(公告)号：US20140268978A1

公开(公告)日：2014-09-18

申请号：US14144470

申请日：2013-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin CHOI ,  Su-A KIM ,  Young-Hoon SON ,  Jung-Ho AHN ,  Hak-Soo YU ,  Jae-Youn YOUN

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/105

Abstract: A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays.

Abstract translation: 半导体存储器件可以包括多个数据输入/输出DQ焊盘和多个第一和第二存储单元阵列。 从多个第一存储器单元阵列中的每一个到相应的DQ焊盘的第一组数据路径的每个路径物理上比从多个第二存储单元阵列中的每一个到相应的第二组数据路径的第二组数据路径的每个路径短 DQ垫。 多个第一存储单元阵列中的每一个是指定的第一速度存取单元阵列，并且多个第二存储单元阵列中的每一个是指定的第二速度存取单元阵列，第二速度比第一速度慢。 多个第一存储单元阵列中的每一个的大小小于多个第二存储单元阵列中的每一个的大小。