公开(公告)号：US20130237019A1

公开(公告)日：2013-09-12

申请号：US13864437

申请日：2013-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Woo PARK ,  Hong-Sun HWANG ,  In-Gyu BAEK ,  Dong-Hyun SOHN

IPC: H01L21/77

CPC classification number: H01L21/77 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/24

Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

Abstract translation: 叠层半导体存储器件包括具有功能电路，多个存储单元阵列层以及至少一个连接层的半导体衬底。 存储单元阵列层堆叠在半导体衬底之上。 连接层堆叠在半导体衬底之上，独立于存储单元阵列层。 连接层将布置在存储单元阵列层上的存储单元选择线电连接到功能电路。

公开(公告)号：US20160012880A1

公开(公告)日：2016-01-14

申请号：US14858140

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yun KIM ,  Jong-Pil SON ,  Su-A KIM ,  Chul-Woo PARK ,  Hong-Sun HWANG

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/408 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Abstract translation: 操作易失性存储器件的方法包括存储弱单元行的地址信息。 根据一些示例，在写入弱单元行之后，在预定时间内对弱单元行执行刷新操作。 根据一些示例，可以以对正常单元行的写恢复时间更长的写恢复时间来执行对弱单元行的写入操作。

公开(公告)号：US20140112086A1

公开(公告)日：2014-04-24

申请号：US14057556

申请日：2013-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Woo PARK ,  Joo-Sun CHOI ,  Hong-Sun HWANG

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/023 ,  G11C29/028 ,  G11C2211/4065

Abstract: A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.

Abstract translation: 用于易失性存储器件的刷新方法包括以具有第一刷新周期的第一刷新率来刷新阵列的第一组行的存储器单元，第一刷新率是具有比第二刷新率更长的刷新周期的较低速率 具有第二刷新周期，其中所述阵列的所述第一组行中的每个存储器单元具有比所述第一刷新周期更长的保持时间; 以及具有第三刷新周期的第三刷新率的阵列的第二组行的刷新存储单元，所述第三刷新率是具有比具有所述第二刷新周期的所述第二刷新率更短的刷新周期的较高速率，其中， 第二组行的每行的至少一个存储单元具有比第三刷新周期长的保留时间并且比第一刷新周期短。 第二刷新周期对应于在易失性存储器件的标准中定义的刷新周期。

公开(公告)号：US20130329478A1

公开(公告)日：2013-12-12

申请号：US13937367

申请日：2013-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo Yu ,  Sang-Bo LEE ,  Hong-Sun HWANG ,  Dong-Hyun SOHN

IPC: G11C5/02 ,  G11C7/22

CPC classification number: G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

Abstract: A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

Abstract translation: 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。