公开(公告)号：US20160155515A1

公开(公告)日：2016-06-02

申请号：US14817212

申请日：2015-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Chul-Woo PARK ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA ,  Seong-Jin JANG

IPC: G11C29/44 ,  G11C29/38 ,  G11C29/42 ,  G11C11/4096

CPC classification number: G11C29/4401 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4096 ,  G11C29/42 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

Abstract translation: 半导体存储器件包括存储单元阵列和测试电路。 测试电路从存储单元阵列读取数据流，配置为在比较数据流中的每个第一单元的比特时，将第一单元中的相应比特作为每个第二单元进行比较，并输出包括通过/失败信息的故障信息信号 数据流和关于数据流的附加信息，在半导体存储器件的测试模式中。

公开(公告)号：US20150067448A1

公开(公告)日：2015-03-05

申请号：US14305095

申请日：2014-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil SON ,  Young-Soo SOHN ,  Uk-Song KANG ,  Chul-Woo PARK ,  Jung-Hwan CHOI ,  Won-Il BAE ,  Kyo-Min SOHN

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract translation: 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。

公开(公告)号：US20180053545A1

公开(公告)日：2018-02-22

申请号：US15594891

申请日：2017-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON

IPC: G11C11/419 ,  G06F11/10 ,  G11C7/18 ,  G11C29/04 ,  G11C7/08

CPC classification number: G11C11/419 ,  G06F11/1048 ,  G11C7/08 ,  G11C7/18 ,  G11C29/04 ,  G11C29/42 ,  G11C2029/0411

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The control logic circuit generates an internal processing mode signal in response to a command from a memory controller. The internal processing circuit selectively performs the internal processing operation on a first set of data read from the memory cell array to output a processing result data, in response to the internal processing mode signal. The error correction circuit performs an error correction code (ECC) encoding on the processing result data to generate a second parity data and stores the processing result data and the second parity data in the memory cell array. The error correction circuit generates the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC.

公开(公告)号：US20160104522A1

公开(公告)日：2016-04-14

申请号：US14874568

申请日：2015-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Chul-Woo PARK ,  Young-Soo SOHN

IPC: G11C11/406 ,  G06F12/02 ,  G11C14/00 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/005 ,  G11C29/28 ,  G11C2029/0409 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data.

Abstract translation: 半导体器件的使用时间管理方法可以包括：（1）测量半导体器件的累积操作时间量，以及当该量达到预定值时，产生单元存储激活信号; （2）重复步骤（1）以产生一个或多个附加单元存储激活信号，由此产生多个单元存储激活信号，其中每个重复步骤的预定值是不同的; （3）存储指示生成单位存储激活信号的每个出现的数据; 和（4）基于累积存储的数据检测半导体器件的使用时间。

公开(公告)号：US20190130991A1

公开(公告)日：2019-05-02

申请号：US16028783

申请日：2018-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil SON ,  Kyo-Min SOHN

IPC: G11C29/42 ,  G11C29/02 ,  G06F11/10 ,  G06F11/22

CPC classification number: G11C29/42 ,  G06F11/1064 ,  G06F11/2215 ,  G11C29/02

Abstract: A semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.

公开(公告)号：US20170148501A1

公开(公告)日：2017-05-25

申请号：US15341245

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Ho-Young SONG

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/40607 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array and a first buffer. The memory cell array includes a plurality of bank arrays. Each of the plurality of bank arrays includes a plurality of memory cells. The memory cell array and the first buffer are configured for performing a first internal read operation, which represents operations of retrieving first data from a first region of the memory cell array and of storing the first data into the first buffer, based on a first read command and a first read address. The first internal read operation is performed based on a deterministic interface in which the first data is stored into the first buffer within a predetermined first duration after the first read command is received and a generation of a first acknowledgement signal is unnecessary after storing the first data into the first buffer is completed.

公开(公告)号：US20140247677A1

公开(公告)日：2014-09-04

申请号：US14081493

申请日：2013-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Uk-Song KANG ,  Jong-Pil SON

IPC: G11C11/4076 ,  G11C29/48

CPC classification number: G11C11/4076 ,  G11C29/842

Abstract: A method of accessing a semiconductor memory is disclosed which includes outputting a row address and an active command to the semiconductor memory; outputting a column address and a read or write command to the semiconductor memory; and outputting a spare access command to the semiconductor memory to access data from a spare memory cell at a timing based on an additive latency of the semiconductor memory. Related devices and systems are also disclosed.

Abstract translation: 公开了一种访问半导体存储器的方法，其包括向半导体存储器输出行地址和有效命令; 向半导体存储器输出列地址和读或写命令; 以及基于所述半导体存储器的附加延迟的定时，向所述半导体存储器输出备用访问命令以从备用存储单元访问数据。 还公开了相关的装置和系统。

公开(公告)号：US20150003141A1

公开(公告)日：2015-01-01

申请号：US14220275

申请日：2014-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Chul-Woo PARK ,  Young-Soo SOHN

IPC: G11C29/00 ,  G11C11/407 ,  G11C17/16

CPC classification number: G11C29/846 ,  G11C17/16 ,  G11C29/785

Abstract: A semiconductor memory device is provided which includes a memory cell group and a fuse cell group including at least one fuse cell to store a failed address corresponding to a defective memory cell in the memory cell group; a spare cell group including a spare memory cell configured to replace the defective memory cell included in the memory cell group; a data sensing/selection circuit configured to read data stored in the memory cell group and the spare cell group in response to an activation of the word line; a fuse sense amplifier configured to read the failed address in response to the activation of the word line; and a repair logic circuit configured to control the data sensing/selection circuit in response to the failed address such that the defective memory cell in the memory cell group is replaced by the spare memory cell.

Abstract translation: 提供了一种半导体存储器件，其包括存储单元组和熔丝单元组，所述熔丝单元组包括至少一个熔丝单元，用于存储与所述存储单元组中的有缺陷存储单元相对应的故障地址; 备用单元组，其包括被配置为替换所述存储单元组中包括的所述有缺陷的存储单元的备用存储单元; 数据感测/选择电路，被配置为响应于字线的激活读取存储在存储单元组和备用单元组中的数据; 熔丝读出放大器，被配置为响应于字线的激活读取失败的地址; 以及修复逻辑电路，被配置为响应于所述故障地址来控制所述数据检测/选择电路，使得所述存储单元组中的所述有缺陷的存储器单元被所述备用存储单元替换。

公开(公告)号：US20140146624A1

公开(公告)日：2014-05-29

申请号：US14087167

申请日：2013-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Uk-Song KANG ,  Chul-Woo PARK ,  Young-Soo SOHN

IPC: G11C29/00

CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.

Abstract translation: 在一个示例实施例中，存储器模块包括多个存储器件和被配置为管理多个存储器件的缓冲器芯片。 缓冲器芯片包括具有错误校正单元的存储器管理单元，该单元被配置为对多个存储器件中的每一个进行纠错操作。 多个存储器设备中的每一个包括至少一个可由存储器管理单元访问的备用列，并且存储器管理单元被配置为通过有选择地使用至少一个备用列来校正多个存储器件的错误， 纠错单元的纠错能力。

公开(公告)号：US20170365361A1

公开(公告)日：2017-12-21

申请号：US15696794

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hoi-Ju CHUNG ,  Jong-Pil SON ,  Kwang-II PARK ,  Seong-Jin JANG

IPC: G11C29/52 ,  G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C11/15 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C11/15 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.