公开(公告)号：US11694965B2

公开(公告)日：2023-07-04

申请号：US17406517

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbo Lee ,  Joonseok Oh ,  Byunglyul Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214

Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

公开(公告)号：US20210118792A1

公开(公告)日：2021-04-22

申请号：US16891663

申请日：2020-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbo Lee ,  Joonseok Oh

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/311 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

Abstract: A fan-out type semiconductor package may include a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a molding member, a first upper RDL, an upper PID and a second upper RDL. The frame may include an insulation substrate having a cavity and a middle RDL formed through the insulation substrate, with the semiconductor chip arranged in the cavity. The first upper RDL may be arranged on an upper surface of the insulation substrate. The first upper RDL may be connected to an upper end of the middle RDL. The upper PID may be formed on upper surfaces of the frame, the semiconductor chip and the molding member. The second upper RDL may be formed in the upper PID. A photolithography process may be applied to the upper PID so that the second upper RDL formed on the upper PID may have a fine pattern.