公开(公告)号：US20240258242A1

公开(公告)日：2024-08-01

申请号：US18421284

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kitae Park ,  Chiwan Song ,  Seungmin Baek ,  Joohyung Lee ,  Joonseok Oh ,  Junghyun Cho

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/20 ,  H01L25/105 ,  H01L25/18 ,  H10B80/00 ,  H01L24/19 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2225/1035 ,  H01L2924/01028 ,  H01L2924/01029

Abstract: A semiconductor package includes a package body, a fan-in-chip structure (FICS) in the package body, a first redistribution structure, and a second redistribution structure. The FICS includes a first chip having a front surface and a rear surface, a bridge wiring structure including a bridge wiring layer on the rear surface of the first chip, and a bridge pad electrically connected to the bridge wiring layer. The first redistribution structure is on a bottom surface of the package body and the front surface of the first chip and includes a first redistribution element. The second redistribution structure is on a top surface of the package body and the rear surface of the first chip and includes a second redistribution element electrically connected to the bridge wiring structure.

公开(公告)号：US11121090B2

公开(公告)日：2021-09-14

申请号：US16683960

申请日：2019-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbo Lee ,  Joonseok Oh ,  Byunglyul Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

公开(公告)号：US20240355709A1

公开(公告)日：2024-10-24

申请号：US18637022

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Seonkyu Kim ,  Seungmin Baek ,  Joonseok Oh ,  Joohyung Lee ,  Junghyun Cho

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1815

Abstract: A semiconductor package includes a base chip, a first semiconductor chip on the base chip, and a first fillet layer between the base chip and the first semiconductor chip. The base chip includes a base substrate, a plurality of through-electrodes penetrating through the base substrate, a protective layer surrounding the plurality of through-electrodes and covering an upper surface of the base substrate, and a plurality of trenches vertically penetrating the protective layer. The plurality of through-electrodes form a transistor area on the base substrate, and the plurality of trenches include first trenches disposed between adjacent through-vias in the transistor area and second trenches disposed in an outer side portion of the transistor area.

公开(公告)号：US20240297122A1

公开(公告)日：2024-09-05

申请号：US18592829

申请日：2024-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyundong Lee ,  Youngmin Kim ,  Minji Kim ,  Joonseok Oh ,  Changbo Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/08 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/08225 ,  H01L2224/16227

Abstract: Provided is a semiconductor package including a first chip, a first chip pad on an upper surface of the first chip, an upper redistribution structure above the first chip, a lowermost via pattern within the upper redistribution structure and non-overlapping with the first chip pad in a vertical direction, and a connection pattern electrically connecting the first chip pad to the lowermost via pattern, wherein the connection pattern overlaps each of the first chip pad and the lowermost via pattern in a vertical direction.

公开(公告)号：US12237252B2

公开(公告)日：2025-02-25

申请号：US17672092

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Jeon ,  Joonseok Oh ,  Youngmin Kim ,  Dongheon Kang ,  Changbo Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.

公开(公告)号：US20240038740A1

公开(公告)日：2024-02-01

申请号：US18329530

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyundong Lee ,  Youngmin Kim ,  Joonseok Oh ,  Sangyun Lee ,  Changbo Lee

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/3107 ,  H01L24/16 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15174

Abstract: A semiconductor package includes a first wiring structure including a plurality of first redistribution patterns having a plurality of first bottom connection pads and a plurality of first top connection pads and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns, a second wiring structure including a plurality of second redistribution patterns having a plurality of second bottom connection pads and a plurality of second top connection pads and a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a semiconductor chip interposed between the first wiring structure and the second wiring structure, an encapsulant filling a space between the first wiring structure and the second wiring structure, and a plurality of connection structures passing through the encapsulant and connecting the plurality of first top connection pads to the plurality of second bottom connection pads and arranged around the semiconductor chip.

公开(公告)号：US11462466B2

公开(公告)日：2022-10-04

申请号：US16891663

申请日：2020-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbo Lee ,  Joonseok Oh

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/311

Abstract: A fan-out type semiconductor package may include a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a molding member, a first upper RDL, an upper PID and a second upper RDL. The frame may include an insulation substrate having a cavity and a middle RDL formed through the insulation substrate, with the semiconductor chip arranged in the cavity. The first upper RDL may be arranged on an upper surface of the insulation substrate. The first upper RDL may be connected to an upper end of the middle RDL. The upper PID may be formed on upper surfaces of the frame, the semiconductor chip and the molding member. The second upper RDL may be formed in the upper PID. A photolithography process may be applied to the upper PID so that the second upper RDL formed on the upper PID may have a fine pattern.

公开(公告)号：US20210384136A1

公开(公告)日：2021-12-09

申请号：US17406517

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbo LEE ,  Joonseok Oh ,  Byunglyul Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: This invention provides a fan-out semiconductor package ,the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

公开(公告)号：US20240321774A1

公开(公告)日：2024-09-26

申请号：US18399519

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Chiwan Song ,  Seonkyu Kim ,  Hyunna Bae ,  Seungmin Baek ,  Yongjae Song ,  Joonseok Oh ,  Jaewook Jung ,  Seokil Hong

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/3205 ,  H01L23/31 ,  H01L23/492 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/32055 ,  H01L23/3135 ,  H01L23/4926 ,  H01L24/48 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: The present disclosure relates to semiconductor devices and semiconductor packages. One example semiconductor device includes a crystalline silicon layer, an amorphous silicon layer on the crystalline silicon layer and extending along a first surface of the crystalline silicon layer, and a dielectric layer on the amorphous silicon layer and extending along a surface of the amorphous silicon layer. The dielectric layer includes silicon oxynitride and has compressive stress.

公开(公告)号：US20240194577A1

公开(公告)日：2024-06-13

申请号：US18239167

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Jeon ,  Youngmin Kim ,  Joonseok Oh ,  Woongkeon Lee ,  Changbo Lee

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/08

Abstract: A semiconductor package includes a first redistribution structure having at least one first redistribution layer and at least one first insulating layer that are alternately stacked, a semiconductor chip electrically connected to the first redistribution structure, a second insulating layer disposed above the semiconductor chip and having an opening, a pad electrically connected to the first redistribution structure, disposed on the second insulating layer, and overlapping the opening, a pad surface layer disposed on a first region of an upper surface of the pad to overlap the opening, the pad surface layer formed of a first conductive material different from a second conductive material forming the pad. The pad has an anchor portion protruding from a second region of the upper surface of the pad. The anchor portion protrudes to a position higher than that of a lower surface of the pad surface layer.