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    SEMICONDUCTOR DEVICE
    2.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240194577A1

    公开(公告)日：2024-06-13

    申请号：US18239167

    申请日：2023-08-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoonyoung Jeon ,  Youngmin Kim ,  Joonseok Oh ,  Woongkeon Lee ,  Changbo Lee

    IPC: H01L23/498 ,  H01L23/31

    CPC classification number: H01L23/49838 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/08

    Abstract: A semiconductor package includes a first redistribution structure having at least one first redistribution layer and at least one first insulating layer that are alternately stacked, a semiconductor chip electrically connected to the first redistribution structure, a second insulating layer disposed above the semiconductor chip and having an opening, a pad electrically connected to the first redistribution structure, disposed on the second insulating layer, and overlapping the opening, a pad surface layer disposed on a first region of an upper surface of the pad to overlap the opening, the pad surface layer formed of a first conductive material different from a second conductive material forming the pad. The pad has an anchor portion protruding from a second region of the upper surface of the pad. The anchor portion protrudes to a position higher than that of a lower surface of the pad surface layer.

    FAN-OUT TYPE SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME
    4.
    发明申请
    FAN-OUT TYPE SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210118792A1

    公开(公告)日：2021-04-22

    申请号：US16891663

    申请日：2020-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changbo Lee ,  Joonseok Oh

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/311 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

    Abstract: A fan-out type semiconductor package may include a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a molding member, a first upper RDL, an upper PID and a second upper RDL. The frame may include an insulation substrate having a cavity and a middle RDL formed through the insulation substrate, with the semiconductor chip arranged in the cavity. The first upper RDL may be arranged on an upper surface of the insulation substrate. The first upper RDL may be connected to an upper end of the middle RDL. The upper PID may be formed on upper surfaces of the frame, the semiconductor chip and the molding member. The second upper RDL may be formed in the upper PID. A photolithography process may be applied to the upper PID so that the second upper RDL formed on the upper PID may have a fine pattern.

    Semiconductor package
    5.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12237252B2

    公开(公告)日：2025-02-25

    申请号：US17672092

    申请日：2022-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoonyoung Jeon ,  Joonseok Oh ,  Youngmin Kim ,  Dongheon Kang ,  Changbo Lee

    IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

    Abstract: A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.

    SEMICONDUCTOR PACKAGE
    6.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240038740A1

    公开(公告)日：2024-02-01

    申请号：US18329530

    申请日：2023-06-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyundong Lee ,  Youngmin Kim ,  Joonseok Oh ,  Sangyun Lee ,  Changbo Lee

    IPC: H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

    CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/3107 ,  H01L24/16 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15174

    Abstract: A semiconductor package includes a first wiring structure including a plurality of first redistribution patterns having a plurality of first bottom connection pads and a plurality of first top connection pads and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns, a second wiring structure including a plurality of second redistribution patterns having a plurality of second bottom connection pads and a plurality of second top connection pads and a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a semiconductor chip interposed between the first wiring structure and the second wiring structure, an encapsulant filling a space between the first wiring structure and the second wiring structure, and a plurality of connection structures passing through the encapsulant and connecting the plurality of first top connection pads to the plurality of second bottom connection pads and arranged around the semiconductor chip.

    Fan-out type semiconductor packages and methods of manufacturing the same
    7.
    发明授权
    Fan-out type semiconductor packages and methods of manufacturing the same 有权

    公开(公告)号：US11462466B2

    公开(公告)日：2022-10-04

    申请号：US16891663

    申请日：2020-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changbo Lee ,  Joonseok Oh

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/311

    Abstract: A fan-out type semiconductor package may include a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a molding member, a first upper RDL, an upper PID and a second upper RDL. The frame may include an insulation substrate having a cavity and a middle RDL formed through the insulation substrate, with the semiconductor chip arranged in the cavity. The first upper RDL may be arranged on an upper surface of the insulation substrate. The first upper RDL may be connected to an upper end of the middle RDL. The upper PID may be formed on upper surfaces of the frame, the semiconductor chip and the molding member. The second upper RDL may be formed in the upper PID. A photolithography process may be applied to the upper PID so that the second upper RDL formed on the upper PID may have a fine pattern.

    Semiconductor device and method of fabricating the same
    9.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US12199060B2

    公开(公告)日：2025-01-14

    申请号：US18143983

    申请日：2023-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changbo Lee ,  Kwanhoo Son ,  Joon Seok Oh

    IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

    INTERCONNECTION STRUCTURE AND METHOD OF FABRICATING THE SAME
    10.
    发明公开
    INTERCONNECTION STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240047357A1

    公开(公告)日：2024-02-08

    申请号：US18307109

    申请日：2023-04-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoonyoung Jeon ,  Youngmin Kim ,  Joon Seok Oh ,  Changbo Lee

    IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L23/53238 ,  H01L23/528 ,  H01L21/76843 ,  H01L21/76802 ,  H01L21/76877

    Abstract: An interconnection structure includes a first dielectric layer, a second dielectric layer, first wiring patterns, and a first conductive pattern. The first wiring patterns respectively include a first penetration part that extends into a surface of the first dielectric layer, a first intervention part on the first penetration part and in the second dielectric layer, and a first connection part on the first intervention part and in the second dielectric layer. A top surface of the first intervention part is at a same level as a top surface of the first conductive pattern relative to the surface of the first dielectric layer. An angle between a sidewall of the first connection part and the top surface of the first intervention part is greater than that between a sidewall of the first penetration part and a bottom surface of the first dielectric layer.

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