公开(公告)号：US20250132228A1

公开(公告)日：2025-04-24

申请号：US18675431

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik Lee ,  Nara Lee ,  Jong-Min Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18

Abstract: A semiconductor chip and a semiconductor package are provided. The semiconductor chip includes a substrate, a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer stacked on the substrate, lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction, third and fourth interlayer insulating layers stacked on the lower pads and the second interlayer insulating layer, an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness, and via structures in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad. Each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping the first via in the vertical direction.

公开(公告)号：US12159859B2

公开(公告)日：2024-12-03

申请号：US17696989

申请日：2022-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin Choi ,  Jeonil Lee ,  Jongmin Lee ,  Juik Lee

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/42 ,  H01L23/48

Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

公开(公告)号：US11362053B2

公开(公告)日：2022-06-14

申请号：US16922828

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyoung Jeong ,  Juik Lee ,  Junghoon Han

IPC: H01L23/00

Abstract: Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

公开(公告)号：US10600791B2

公开(公告)日：2020-03-24

申请号：US16125167

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Wan Kim ,  Keunnam Kim ,  Juik Lee

IPC: H01L27/108 ,  H01L27/22 ,  G11C8/08 ,  H01L23/535 ,  H01L27/24 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line buried in an upper portion of a substrate and extending in a first direction, and a word line contact plug connected to the word line. An end portion of the word line includes a contact surface exposed in the first direction, and the word line contact plug is connected to the contact surface.

公开(公告)号：US10026694B2

公开(公告)日：2018-07-17

申请号：US15608747

申请日：2017-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Sooho Shin ,  Juik Lee ,  Jun Ho Lee ,  Kwangmin Kim ,  Ilyoung Moon ,  Jemin Park ,  Bumseok Seo ,  Chan-Sic Yoon ,  Hoin Lee

IPC: H01L23/544 ,  H01L27/108

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.