公开(公告)号：US20250132228A1

公开(公告)日：2025-04-24

申请号：US18675431

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik Lee ,  Nara Lee ,  Jong-Min Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18

Abstract: A semiconductor chip and a semiconductor package are provided. The semiconductor chip includes a substrate, a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer stacked on the substrate, lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction, third and fourth interlayer insulating layers stacked on the lower pads and the second interlayer insulating layer, an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness, and via structures in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad. Each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping the first via in the vertical direction.

公开(公告)号：US20240145317A1

公开(公告)日：2024-05-02

申请号：US18210114

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon Shin ,  Jongmin Lee ,  Sungyun Woo ,  Nara Lee ,  Yeonjin Lee ,  Jimin Choi

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/481 ,  H01L24/05 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/014

Abstract: A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.

公开(公告)号：US20250062255A1

公开(公告)日：2025-02-20

申请号：US18670055

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong PARK ,  Jongmin Lee ,  Nara Lee ,  Juik Lee

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor chip includes a semiconductor substrate including an active surface and an inactive surface opposite to the active surface, a wiring layer on the active surface, a front connection pad on the wiring layer, a lower protective insulating layer at least partially covering the wiring layer and including a lower opening that exposes at least a portion of the front connection pad, an upper protective insulating layer including an upper opening communicatively coupled to the lower opening on the lower protective insulating layer, a connection terminal coupled to the front connection pad through the lower opening and the upper opening, and an upper cover insulating layer between the connection terminal and the upper protective insulating layer. The upper protective insulating layer includes an organic material. The upper cover insulating layer includes an inorganic material.