ADDRESS RE-ORDERING MECHANISM FOR EFFICIENT PRE-FETCH TRAINING IN AN OUT-OF-ORDER PROCESSOR
    11.
    发明申请
    ADDRESS RE-ORDERING MECHANISM FOR EFFICIENT PRE-FETCH TRAINING IN AN OUT-OF-ORDER PROCESSOR 有权
    寻求在订单处理器中进行有效预先培训的重新订购机制

    公开(公告)号:US20150278100A1

    公开(公告)日:2015-10-01

    申请号:US14498878

    申请日:2014-09-26

    Abstract: A computing system includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction in an out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

    Abstract translation: 计算系统包括:指令调度模块,被配置为接收程序指令; 耦合到指令调度模块的地址重排序模块,被配置为当所述程序指令是预取过滤器中的高速缓存行中的命中时对所述程序指令进行过滤。 计算机系统还包括:指令调度模块,被配置为接收程序指令; 一个地址重排序模块,耦合到指令调度模块,被配置为:以程序顺序在程序指令的标签模块中分配标签,在虚拟地址模块中为程序指令分配虚拟地址, 相对于程序顺序的顺序,并插入与标签相关联的指针,以将标签链接到虚拟地址。

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