Abstract:
A touchscreen controller includes a first sample-and-hold (S/H) block configured to sample a plurality of capacitive touch inputs in response to a first sampling signal and to output samples of the sampled capacitive touch inputs in response to first output control signals, a second S/H block configured to sample a plurality of force touch inputs in response to a second sampling signal independent of the first sampling signal and to output samples of the sampled force touch inputs in response to second output control signals, and an analog-digital converter (ADC) shared by the first and second S/H blocks and configured to convert the samples of the capacitive touch inputs and the samples of the force touch inputs into digital signals.
Abstract:
Disclosed is a fifth generation (5G) or pre-5G communication system for supporting higher data transmission rates beyond fourth generation (4G) communication systems such as LTE systems. A data communication method includes receiving information about a reception rate of a signal from a second user equipment (UE) performing device-to-device (D2D) communication with a first UE, receiving location information about at least one of the first UE and the second UE, determining a data communication configuration for the D2D communication based on the reception rate information and the location information, and transmitting the determined data communication configuration to at least one of the first UE and the second UE.
Abstract:
A programmable gain amplifier (PGA) circuit includes a first input resistor coupled between a first input node and a first summing node and a second input resistor coupled between a second input node and a second summing node. The PGA circuit further includes a first variable reference resistor coupled between a third input node and the first summing node, a second variable reference resistor coupled between a fourth input node and the second summing node, and an operational amplifier having first and second inputs coupled to respective ones of the first and second summing nodes and first and second outputs coupled to respective ones of the first and second output nodes. At least of the first and second reference resistors may include an R-2R ladder circuit.