公开(公告)号：US12073302B2

公开(公告)日：2024-08-27

申请号：US18219904

申请日：2023-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US12015429B2

公开(公告)日：2024-06-18

申请号：US17969671

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Lei Wang ,  Joseph H. Hassoun

IPC: H03M7/30 ,  G06F9/30 ,  G06F9/38 ,  H03M7/40 ,  H04L5/02

CPC classification number: H03M7/3066 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3818 ,  G06F9/3851 ,  H03M7/40 ,  H03M7/6005 ,  H03M7/6011 ,  H03M7/6023 ,  H04L5/023

Abstract: A multichannel data packer includes a plurality of two-input multiplexers and a controller. The plurality of two-input multiplexers is arranged in 2N rows and N columns in which N is an integer greater than 1. Each input of a multiplexer in a first column receives a respective bit stream of 2N channels of bit streams. Each respective bit stream includes a bit-stream length based on data in the bit stream. The multiplexers in a last column output 2N channels of packed bit streams each having a same bit-stream length. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2N channels of bit streams that each has the same bit-stream length.

公开(公告)号：US11816149B2

公开(公告)日：2023-11-14

申请号：US17171117

申请日：2021-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dafeng Zhang ,  Yanchao Li ,  Yanjun Gao ,  Lei Wang ,  Zhezhu Jin ,  Yingying Jiang ,  Lanlan Zhang

IPC: G06F16/583 ,  G06F18/25 ,  G06V10/762 ,  G06F16/58

CPC classification number: G06F16/583 ,  G06F16/5854 ,  G06F18/251 ,  G06V10/7625 ,  G06V10/7635 ,  G06F16/5866

Abstract: An electronic device and a method for controlling thereof are provided. A method for controlling an electronic device according to the disclosure includes obtaining a plurality of images for performing clustering, obtaining a plurality of target areas corresponding to each of the plurality of images, obtaining a plurality of feature vectors corresponding to the plurality of target areas, obtaining a plurality of central nodes corresponding to the plurality of feature vectors, obtaining neighbor nodes associated with each of the plurality of central nodes, obtaining a subgraph based on the plurality of central nodes and the neighbor nodes, identifying the connection probabilities between the plurality of central nodes of the subgraph and the neighbor nodes of each of the plurality of central nodes based on a graph convolutional network, and clustering the plurality of target areas based on the identified connection probabilities.

公开(公告)号：US11755956B2

公开(公告)日：2023-09-12

申请号：US17257665

申请日：2019-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lei Wang

IPC: G06T15/04 ,  G06N20/00 ,  G06T7/70 ,  G06N3/08 ,  G06T17/00 ,  G06T19/00 ,  G06T19/20 ,  G06V20/40 ,  G06F18/23 ,  G06F18/24 ,  G06F18/213 ,  G06N3/045

CPC classification number: G06N20/00 ,  G06F18/213 ,  G06F18/23 ,  G06F18/24 ,  G06N3/045 ,  G06N3/08 ,  G06T7/70 ,  G06T15/04 ,  G06T17/00 ,  G06T19/006 ,  G06T19/20 ,  G06V20/46 ,  G06T2200/08 ,  G06T2207/20084 ,  G06T2207/30244 ,  G06T2219/2012

Abstract: Provided are a method, a storage medium and an apparatus for converting a 2D picture set to a 3D model. The method includes: identifying the category of each object contained in each picture in the 2D picture set and outline information of each object by using a deep learning algorithm; extracting detail characteristic information of each object in each picture in the 2D picture set by using a computer vision algorithm, wherein the detail feature information at least includes texture information, color feature information and shape feature information of each object; matching the 3D model based on the category, the shape feature information and the outline information of each object, wherein the 3D model matched successfully is the 3D model of the object; and mapping the texture information and the color feature information of each object onto the 3D model of each object.

公开(公告)号：US11621724B2

公开(公告)日：2023-04-04

申请号：US16847642

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Lei Wang

IPC: H04L5/02 ,  G06F9/30 ,  H03M7/30 ,  H03M7/40 ,  G06F9/38

Abstract: A data-sparsity homogenizer includes a plurality of multiplexers and a controller. The plurality of multiplexers receives 2N bit streams of non-homogenous sparse data in which the non-homogenous sparse data includes non-zero value data clumped together. The plurality of multiplexers is arranged in 2N rows and N columns. Each input of a multiplexer in a first column receives a respective bit stream of the 2N bit streams of non-homogenized sparse data, and the multiplexers in a last column output 2N bit streams of sparse data that is more homogenous than the non-homogenous sparse data of the 2N bit streams. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2N channels of bit streams of sparse data that is more homogeneous than the non-homogenous sparse data of the 2N bit streams.

公开(公告)号：US20250103468A1

公开(公告)日：2025-03-27

申请号：US18738220

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo Youn Park ,  Chung Woo Park ,  Chang Yong Park ,  Gang Li ,  Lei Wang

IPC: G06F11/36 ,  G06F11/07

Abstract: A system on chip comprises a first core cluster including a plurality of cores and executing a first virtual machine including a first debug client, and a second core cluster including a plurality of cores and executing a second virtual machine including a second debug client. A first core of the first core cluster and a second core of the second cluster execute a hypervisor at a first exception level and detect unusual operation cores in each cluster. The first core and second core execute the debug server at the first exception level and call the debug clients. The first core and second core execute the debug clients at a second exception level and output stack information of the unusual operation cores.

公开(公告)号：US12133156B2

公开(公告)日：2024-10-29

申请号：US17490408

申请日：2021-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanru Wang ,  Xiaoning Ma ,  Hong Wang ,  Lixiang Xu ,  Weiwei Wang ,  Lei Wang

IPC: H04W40/24 ,  H04W28/06 ,  H04W40/12

CPC classification number: H04W40/248 ,  H04W28/06 ,  H04W40/12

Abstract: A method and a base station for determining transmission paths are provided. The method includes determining that multiple transmission paths are to be configured for each of one or more terminals, and determining first configuration information of a terminal group corresponding to each terminal, which is used for configuring multiple transmission paths for a terminal in the terminal group. The disclosure reduces the complexity and computation amount of configuring transmission paths and improves the system performance.

公开(公告)号：US20230351151A1

公开(公告)日：2023-11-02

申请号：US18219904

申请日：2023-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/08 ,  G06N3/04 ,  G06F17/16 ,  G06T9/00 ,  G06F17/15

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11775256B2

公开(公告)日：2023-10-03

申请号：US18096559

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang

IPC: G06F7/487 ,  G06F7/523 ,  G06F9/30

CPC classification number: G06F7/4876 ,  G06F7/523 ,  G06F9/3001 ,  G06F9/30021

Abstract: An N×N multiplier may include a N/2×N first multiplier, a N/2×N/2 second multiplier, and a N/2×N/2 third multiplier. The N×N multiplier receives two operands to multiply. The first, second and/or third multipliers are selectively disabled if an operand equals zero or has a small value. If the operands are both less than 2N/2, the second or the third multiplier are used to multiply the operands. If one operand is less than 2N/2 and the other operand is equal to or greater than 2N/2, the first multiplier is used or the second and third multipliers are used to multiply the operands. If both operands are equal to or greater than 2N/2, the first, second and third multipliers are used to multiply the operands.

公开(公告)号：US11664819B2

公开(公告)日：2023-05-30

申请号：US16847642

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Lei Wang

IPC: H04L5/02 ,  G06F9/30 ,  H03M7/30 ,  H03M7/40 ,  G06F9/38

CPC classification number: H03M7/3066 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3818 ,  G06F9/3851 ,  H03M7/40 ,  H03M7/6005 ,  H03M7/6011 ,  H03M7/6023 ,  H04L5/023

Abstract: A data-sparsity homogenizer includes a plurality of multiplexers and a controller. The plurality of multiplexers receives 2N bit streams of non-homogenous sparse data in which the non-homogenous sparse data includes non-zero value data clumped together. The plurality of multiplexers is arranged in 2N rows and N columns. Each input of a multiplexer in a first column receives a respective bit stream of the 2N bit streams of non-homogenized sparse data, and the multiplexers in a last column output 2N bit streams of sparse data that is more homogenous than the non-homogenous sparse data of the 2N bit streams. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2N channels of bit streams of sparse data that is more homogeneous than the non-homogenous sparse data of the 2N bit streams.