公开(公告)号：US20240074157A1

公开(公告)日：2024-02-29

申请号：US18336340

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk HWANG ,  Sanghoon UHM ,  Minhee CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05

Abstract: A semiconductor device may include a bit line on a substrate, a gate electrode over the bit line and spaced apart from the bit line, a gate insulation pattern on a sidewall of the gate electrode, a channel on a sidewall of the gate insulation pattern and including an oxide semiconductor material, a conductive pattern contacting an upper surface of the channel and including an amorphous oxide semiconductor material, and a contact plug contacting an upper surface of the conductive pattern. The contact plug may include a metal. The amorphous oxide semiconductor material may include fluorine (F), chlorine (Cl), nitrogen (N), hydrogen (H), or argon (Ar).

公开(公告)号：US20210159231A1

公开(公告)日：2021-05-27

申请号：US16991661

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu LEE ,  Kiseok LEE ,  Woobin SONG ,  Minhee CHO

IPC: H01L27/108 ,  G11C11/4094 ,  G11C11/408

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.