公开(公告)号：US20240276710A1

公开(公告)日：2024-08-15

申请号：US18362998

申请日：2023-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon UHM ,  Min Hee CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes: a substrate; a bit line above the substrate; a channel pattern on the bit line extending in a direction perpendicular to an upper surface of the bit line; a word line intersecting the bit line and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; an insulating pattern on the word line; and a landing pad connected to the channel pattern. The channel pattern includes first, second, and third channel patterns that are sequentially stacked, the first channel pattern is connected to the bit line, the second channel pattern is between the first channel pattern and the third channel pattern, the third channel pattern is connected to the landing pad, the first channel pattern and the third channel pattern include a crystalline oxide semiconductor material, and the second channel pattern includes an amorphous oxide semiconductor material.

公开(公告)号：US20240244831A1

公开(公告)日：2024-07-18

申请号：US18239268

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggeun SONG ,  Sanghoon UHM ,  Yongjin LEE ,  Min Hee CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device includes a bit line extending in a first direction on a substrate. A first insulating pattern is disposed on the bit line. A channel pattern is disposed on an upper side of the bit line and a lateral side of the first insulating pattern. The channel pattern includes an oxide semiconductor material. A gate insulating pattern is disposed on the channel pattern. Word lines are disposed on the gate insulating pattern. A second insulating pattern is disposed on the word lines. A landing pad is disposed on the channel pattern. An interlayer insulating layer disposed between the bit line and the channel pattern.

公开(公告)号：US20240282833A1

公开(公告)日：2024-08-22

申请号：US18364612

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon UHM ,  Min Hee CHO ,  Wonsok LEE ,  Wooje JUNG

IPC: H01L29/423 ,  H01L29/51 ,  H10B12/00

CPC classification number: H01L29/42364 ,  H01L29/518 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device may include a bit line on the substrate, a channel pattern on the bit line and extending in a direction perpendicular to the bit line, a word line intersecting the bit line and spaced apart from the channel pattern, a gate insulating pattern between the channel pattern and the word line, an insulating pattern on the word line, and a landing pad connected to the channel pattern. The gate insulating pattern may include a first gate insulating pattern and a second gate insulating pattern having a first dielectric constant and a second dielectric constant, respectively. The second gate insulating pattern may be between the first gate insulating pattern and the word line. The first and second dielectric constants may be different. A first width of the first gate insulating pattern may be different from a second width of the second gate insulating pattern.

公开(公告)号：US20240250169A1

公开(公告)日：2024-07-25

申请号：US18420969

申请日：2024-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  Sanghoon UHM ,  Minhee CHO ,  Daewon HA

IPC: H01L29/78 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern having a vertical active portion extending in a vertical direction and a first bend portion bent from an upper region of the vertical active portion; a gate electrode spaced apart from the active pattern, wherein at least a portion thereof faces the vertical active portion; an etch stop layer in which at least a portion thereof is disposed between an upper surface of the gate electrode and the first bend portion; a dielectric layer in which at least a portion thereof is disposed between the active pattern and the gate electrode; and a contact plug disposed on the etch stop layer and at least penetrating through the first bend portion.

公开(公告)号：US20240074157A1

公开(公告)日：2024-02-29

申请号：US18336340

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk HWANG ,  Sanghoon UHM ,  Minhee CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05

Abstract: A semiconductor device may include a bit line on a substrate, a gate electrode over the bit line and spaced apart from the bit line, a gate insulation pattern on a sidewall of the gate electrode, a channel on a sidewall of the gate insulation pattern and including an oxide semiconductor material, a conductive pattern contacting an upper surface of the channel and including an amorphous oxide semiconductor material, and a contact plug contacting an upper surface of the conductive pattern. The contact plug may include a metal. The amorphous oxide semiconductor material may include fluorine (F), chlorine (Cl), nitrogen (N), hydrogen (H), or argon (Ar).