公开(公告)号：US20210280230A1

公开(公告)日：2021-09-09

申请号：US17330828

申请日：2021-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Woobin SONG ,  Hyunmog PARK ,  Sangkil LEE

IPC: G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20210159231A1

公开(公告)日：2021-05-27

申请号：US16991661

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu LEE ,  Kiseok LEE ,  Woobin SONG ,  Minhee CHO

IPC: H01L27/108 ,  G11C11/4094 ,  G11C11/408

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

公开(公告)号：US20230021071A1

公开(公告)日：2023-01-19

申请号：US17949305

申请日：2022-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Woobin SONG ,  Hyunmog PARK ,  Sangkil LEE

IPC: G11C11/00 ,  H01L27/108 ,  H01L27/1159 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20220328492A1

公开(公告)日：2022-10-13

申请号：US17847861

申请日：2022-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu LEE ,  Kiseok LEE ,  Woobin SONG ,  Minhee CHO

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

公开(公告)号：US20210159340A1

公开(公告)日：2021-05-27

申请号：US17144444

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woobin SONG ,  Heiseung KIM ,  Mirco CANTORO ,  Sangwoo LEE ,  Minhee CHO ,  Beomyong HWANG

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/161

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.