公开(公告)号：US20210280230A1

公开(公告)日：2021-09-09

申请号：US17330828

申请日：2021-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Woobin SONG ,  Hyunmog PARK ,  Sangkil LEE

IPC: G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20230009575A1

公开(公告)日：2023-01-12

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee CHO ,  Mintae RYU ,  Sungwon YOO ,  Wonsok LEE ,  Hyunmog PARK ,  Kiseok LEE

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US20220328492A1

公开(公告)日：2022-10-13

申请号：US17847861

申请日：2022-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu LEE ,  Kiseok LEE ,  Woobin SONG ,  Minhee CHO

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

公开(公告)号：US20210159340A1

公开(公告)日：2021-05-27

申请号：US17144444

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woobin SONG ,  Heiseung KIM ,  Mirco CANTORO ,  Sangwoo LEE ,  Minhee CHO ,  Beomyong HWANG

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/161

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

公开(公告)号：US20240170578A1

公开(公告)日：2024-05-23

申请号：US18378170

申请日：2023-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungbeck LEE ,  Mintae RYU ,  Minjin KWON ,  Hyeonjeong SUN ,  Wonsok LEE ,  Minhee CHO

IPC: H01L29/786 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/0688 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device includes: a first insulation layer disposed on a substrate; a lower gate pattern disposed on the first insulation layer; a second insulation layer covering at least a portion of the lower gate pattern; a first lower gate insulation layer disposed on the lower gate pattern and the second insulation layer; a source pattern and a drain pattern disposed on the first lower gate insulation layer, wherein the source pattern and the drain pattern are spaced apart from each other to include a trench facing the lower gate pattern; an oxide semiconductor layer formed along surfaces of the source and drain patterns and a bottom surface of the trench; an upper gate insulation layer disposed on the oxide semiconductor layer; and an upper gate pattern disposed on the upper gate insulation layer and filling the trench.

公开(公告)号：US20230021071A1

公开(公告)日：2023-01-19

申请号：US17949305

申请日：2022-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Woobin SONG ,  Hyunmog PARK ,  Sangkil LEE

IPC: G11C11/00 ,  H01L27/108 ,  H01L27/1159 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20210217897A1

公开(公告)日：2021-07-15

申请号：US17004427

申请日：2020-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Hyunmog Park ,  Minwoo Song ,  Woobin Song ,  Hyunsil Oh ,  Minsu Lee

IPC: H01L29/786 ,  H01L27/12

Abstract: A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure and continuously arranged on a top surface of the substrate in the active region and the device isolation region; a gate structure arranged on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and a source/drain region arranged on both sides of the gate structure and formed in the oxide semiconductor layer, in which, when viewed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.

公开(公告)号：US20250063727A1

公开(公告)日：2025-02-20

申请号：US18680554

申请日：2024-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHO ,  Hyeran LEE ,  Masayuki TERAI

IPC: H10B12/00 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes an upper conductive line extending in a first horizontal direction over a substrate, a channel layer facing the upper conductive line in a second horizontal direction that is perpendicular to the first horizontal direction, a gate dielectric film between the channel layer and the upper conductive line, a conductive contact pattern including a lower surface, which is in contact with an upper surface of the channel layer, and sidewalls including a first sidewall, which faces the upper conductive line in the second horizontal direction, and an insulating spacer including a first portion between the upper conductive line and the conductive contact pattern in the second horizontal direction.

公开(公告)号：US20240322048A1

公开(公告)日：2024-09-26

申请号：US18606081

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Jeonil LEE ,  Minhee CHO ,  Daweon HA

IPC: H01L29/792 ,  H10B12/00

CPC classification number: H01L29/7926 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: Provided is an integrated circuit device including a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction, disposed on the source line, and having a first sidewall and a second sidewall, a trapping layer on the first sidewall of the channel layer and including an oxide semiconductor, a word line on at least one sidewall of the trapping layer and extending in a second horizontal direction crossing the first horizontal direction, a gate insulation layer between the at least one sidewall of the trapping layer and the word line, and a bit line electrically connected to the channel layer and extending in the first horizontal direction, wherein the channel layer has a first bandgap energy, and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.

公开(公告)号：US20240250169A1

公开(公告)日：2024-07-25

申请号：US18420969

申请日：2024-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  Sanghoon UHM ,  Minhee CHO ,  Daewon HA

IPC: H01L29/78 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern having a vertical active portion extending in a vertical direction and a first bend portion bent from an upper region of the vertical active portion; a gate electrode spaced apart from the active pattern, wherein at least a portion thereof faces the vertical active portion; an etch stop layer in which at least a portion thereof is disposed between an upper surface of the gate electrode and the first bend portion; a dielectric layer in which at least a portion thereof is disposed between the active pattern and the gate electrode; and a contact plug disposed on the etch stop layer and at least penetrating through the first bend portion.