公开(公告)号：US20200227519A1

公开(公告)日：2020-07-16

申请号：US16545906

申请日：2019-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-bin SONG ,  Hei-seung KIM ,  Mirco CANTORO ,  Sang-woo LEE ,  Min-hee CHO ,  Beom-yong HWANG

IPC: H01L29/06 ,  H01L29/22 ,  H01L29/786

Abstract: A semiconductor device includes a channel layer located on a substrate, the channel layer including a conductive oxide, a gate structure located on the channel layer, the gate structure including a gate electrode and gate spacers located on both sidewalls of the gate electrode, and source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer. The source and drain regions are configured to apply tensile stress to a portion of the channel layer located under the gate structure.

公开(公告)号：US20190189778A1

公开(公告)日：2019-06-20

申请号：US16284843

申请日：2019-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil PARK ,  Changhee KIM ,  Yunil LEE ,  Mirco CANTORO ,  Junggun YOU ,  Donghun LEE

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

公开(公告)号：US20180269333A1

公开(公告)日：2018-09-20

申请号：US15981578

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco CANTORO ,  Yeon-cheol HEO ,  Maria Toledano LUQUE

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642

Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

公开(公告)号：US20170294437A1

公开(公告)日：2017-10-12

申请号：US15409202

申请日：2017-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco CANTORO ,  YeonCheol HEO

IPC: H01L27/092 ,  H01L29/267 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L27/11 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.