公开(公告)号：US20230371265A1

公开(公告)日：2023-11-16

申请号：US18136993

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Myunghun Woo ,  Yongseok Kim

IPC: H10B51/20 ,  H10B51/10 ,  H01L29/417 ,  H01L29/51

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L29/41725 ,  H01L29/516

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a conductive layer on a substrate; an insulating isolation layer on the conductive layer; a stack structure on the insulating isolation layer, the stack structure including a plurality of source/drain contact layers and a plurality of gate electrode layers alternately provided along a first direction, perpendicular to an upper surface of the substrate; a vertical channel layer extending through the stack structure and the insulating isolation layer, wherein the vertical channel layer is in contact with each of the plurality of source/drain contact layers, and is connected to the conductive layer; and a gate insulating layer between each of the plurality of gate electrode layers and the vertical channel layer.

公开(公告)号：US11778825B2

公开(公告)日：2023-10-03

申请号：US17702967

申请日：2022-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Doohee Hwang

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

公开(公告)号：US11315946B2

公开(公告)日：2022-04-26

申请号：US16838106

申请日：2020-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Doohee Hwang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11524

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.