公开(公告)号：US11563028B2

公开(公告)日：2023-01-24

申请号：US17034733

申请日：2020-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seo-Goo Kang ,  Hyo Joon Ryu ,  Sang Youn Jo ,  Jee Hoon Han

IPC: H01L27/11582 ,  H01L25/18 ,  H01L23/535 ,  H01L25/065 ,  H01L23/00 ,  H01L23/532

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

公开(公告)号：US11211402B2

公开(公告)日：2021-12-28

申请号：US16750176

申请日：2020-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seo-Goo Kang ,  Younghwan Son ,  Kwonsoon Jo

IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  G11C8/14

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.

公开(公告)号：US12200936B2

公开(公告)日：2025-01-14

申请号：US18492504

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Jee Hoon Han ,  Seo-Goo Kang ,  Hyo Joon Ryu

IPC: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.

公开(公告)号：US20240422983A1

公开(公告)日：2024-12-19

申请号：US18404198

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Seo-Goo Kang ,  Seunghyun Lee ,  Jeehoon Han

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device and an electronic system are provided. The semiconductor device may include a substrate including a cell array region and a connection region, a stacked structure including conductive patterns stacked on the substrate, an inner supporter that extends into the stacked structure in the connection region, a contact plug that extends into a portion of the stacked structure and electrically connected to one of the conductive patterns and at least partially extends around the inner supporter in plan view, an insulating spacer between the contact plug and the stacked structure and at least partially extends around the contact plug, and outer supporters spaced apart from the contact plug in the connection region and extending into the stacked structure.

公开(公告)号：US11864384B2

公开(公告)日：2024-01-02

申请号：US17579656

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je Suk Moon ,  Seo-Goo Kang ,  Young Hwan Son ,  Kohji Kanamori ,  Jee Hoon Han

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

公开(公告)号：US11502101B2

公开(公告)日：2022-11-15

申请号：US17022525

申请日：2020-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Jee Hoon Han ,  Seo-Goo Kang ,  Hyo Joon Ryu

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  G11C8/14 ,  H01L27/11526 ,  H01L27/11556 ,  G11C7/18 ,  H01L27/11519

Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.

公开(公告)号：US11233065B2

公开(公告)日：2022-01-25

申请号：US16718498

申请日：2019-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je Suk Moon ,  Seo-Goo Kang ,  Young Hwan Son ,  Kohji Kanamori ,  Jee Hoon Han

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11565

Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

公开(公告)号：US20190139979A1

公开(公告)日：2019-05-09

申请号：US16018199

申请日：2018-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KOHJI KANAMORI ,  Seo-Goo Kang ,  Younghwan Son ,  Kwonsoon Jo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  G11C8/14

CPC classification number: H01L27/11582 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.