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公开(公告)号:US20240224525A1
公开(公告)日:2024-07-04
申请号:US18608383
申请日:2024-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyo Joon Ryu , Young Hwan Son , Seo-Goo Kang , Jung Hoon Jun , Kohji Kanamori , Jee Hoon Han
IPC: H10B43/27 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/40
CPC classification number: H10B43/27 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/40
Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
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公开(公告)号:US11581331B2
公开(公告)日:2023-02-14
申请号:US17101401
申请日:2020-11-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyo Joon Ryu , Young Hwan Son , Seo-Goo Kang , Jung Hoon Jun , Kohji Kanamori , Jee Hoon Han
IPC: H01L27/11582 , H01L23/535 , H01L27/11573 , H01L27/11529 , H01L27/11556
Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
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公开(公告)号:US10714495B2
公开(公告)日:2020-07-14
申请号:US16108294
申请日:2018-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kwonsoon Jo , Seo-Goo Kang , Younghwan Son , Kohji Kanamori
IPC: H01L27/11582 , H01L27/1157 , H01L23/532 , G11C7/14 , G11C7/18 , H01L27/11573 , H01L27/11565 , G11C16/00 , H01L27/11575 , G11C5/02
Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure including a plurality of peripheral logic circuits disposed on a semiconductor substrate, a horizontal semiconductor layer disposed on the peripheral logic structure, an electrode structure including a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer, and a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and including a through-plug connected to the peripheral logic structure. A sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance. A sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.
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公开(公告)号:US20240057336A1
公开(公告)日:2024-02-15
申请号:US18492504
申请日:2023-10-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kohji Kanamori , Jee Hoon Han , Seo-Goo Kang , Hyo Joon Ryu
CPC classification number: H10B43/27 , G11C8/14 , G11C7/18 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.
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公开(公告)号:US10707231B2
公开(公告)日:2020-07-07
申请号:US16193283
申请日:2018-11-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyeong Jin Park , Seo-Goo Kang , Kwonsoon Jo , Kohji Kanamori
IPC: H01L27/11582 , H01L27/11573 , H01L23/48 , H01L27/11568 , H01L23/528 , H01L23/522 , H01L29/10
Abstract: Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.
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公开(公告)号:US10566345B2
公开(公告)日:2020-02-18
申请号:US16018199
申请日:2018-06-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kohji Kanamori , Seo-Goo Kang , Younghwan Son , Kwonsoon Jo
IPC: H01L27/11 , H01L27/11582 , H01L27/1157 , H01L27/11573 , G11C8/14
Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.
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公开(公告)号:US20190172838A1
公开(公告)日:2019-06-06
申请号:US16108294
申请日:2018-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kwonsoon Jo , Seo-Goo Kang , Younghwan Son , Kohji Kanamori
IPC: H01L27/11582 , H01L27/1157 , H01L27/11573 , G11C7/14 , G11C7/18 , H01L23/532
Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure including a plurality of peripheral logic circuits disposed on a semiconductor substrate, a horizontal semiconductor layer disposed on the peripheral logic structure, an electrode structure including a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer, and a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and including a through-plug connected to the peripheral logic structure. A sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance. A sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.
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公开(公告)号:US11963358B2
公开(公告)日:2024-04-16
申请号:US18104328
申请日:2023-02-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyo Joon Ryu , Young Hwan Son , Seo-Goo Kang , Jung Hoon Jun , Kohji Kanamori , Jee Hoon Han
IPC: H10B43/27 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/40
CPC classification number: H10B43/27 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/40
Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
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公开(公告)号:US11963357B2
公开(公告)日:2024-04-16
申请号:US18065799
申请日:2022-12-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kohji Kanamori , Seo-Goo Kang , Hyo Joon Ryu , Sang Youn Jo , Jee Hoon Han
IPC: H10B43/27 , H01L23/00 , H01L23/532 , H01L23/535 , H01L25/065 , H01L25/18
CPC classification number: H10B43/27 , H01L23/53223 , H01L23/53261 , H01L23/535 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.
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公开(公告)号:US11856778B2
公开(公告)日:2023-12-26
申请号:US17983007
申请日:2022-11-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kohji Kanamori , Jee Hoon Han , Seo-Goo Kang , Hyo Joon Ryu
CPC classification number: H10B43/27 , G11C7/18 , G11C8/14 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.
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