公开(公告)号：US09385699B2

公开(公告)日：2016-07-05

申请号：US14719406

申请日：2015-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk Lim ,  Jae-Jin Park ,  Seung-Hoon Lee

IPC: H03L7/06 ,  H03K5/135 ,  H03L7/081 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00013 ,  H03L7/0812

Abstract: A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell.

Abstract translation: 延迟单元包括第一晶体管和第二晶体管，其中至少一个具有完全耗尽的绝缘体上硅（FD-SOI）结构。 第一控制电压被施加到第一晶体管的主体，并且第二控制电压被施加到第二晶体管的主体，以便调整延迟单元的延迟时间。 DLL和PLL电路包括这种类型的延迟单元。