公开(公告)号：US10114548B2

公开(公告)日：2018-10-30

申请号：US15690379

申请日：2017-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G06F3/06 ,  G11C8/10 ,  G11C7/10 ,  G11C8/18 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US09754649B2

公开(公告)日：2017-09-05

申请号：US15180175

申请日：2016-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C7/22 ,  G11C8/18 ,  G11C8/06 ,  G11C8/10 ,  G06F3/06 ,  G11C7/10

CPC classification number: G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.