公开(公告)号：US20230223065A1

公开(公告)日：2023-07-13

申请号：US18070741

申请日：2022-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhaeng KANG ,  Kyomin SOHN

IPC: G11C11/22

CPC classification number: G11C11/2257 ,  G11C11/2275

Abstract: Disclosed is a memory device which includes a plurality of memory banks and control logic. The control logic receives a plurality of column address bits and a plurality of read commands. The control logic includes a processing-in-memory (PIM) address generator. In a first operation mode, the control logic sends the plurality of column address bits to a memory bank. In a second operation mode, when the PIM address generator receives a first read command of the plurality of read commands, the control logic sends, to the memory bank, a first PIM address generated based on remaining column address bits other than some column address bits of the plurality of column address bits.

公开(公告)号：US20220107803A1

公开(公告)日：2022-04-07

申请号：US17314476

申请日：2021-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan RO ,  Shinhaeng KANG ,  Seongil O ,  Seungwoo SEO

IPC: G06F9/30 ,  G06F9/50 ,  G06F13/16 ,  H03K19/173

Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

公开(公告)号：US20220310194A1

公开(公告)日：2022-09-29

申请号：US17840722

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Joonho SONG ,  Seungwon LEE

IPC: G11C29/00 ,  G06F11/20 ,  G06F12/0815 ,  G11C29/38 ,  H01L25/065 ,  H01L25/18 ,  G01R31/3193

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

公开(公告)号：US20220292033A1

公开(公告)日：2022-09-15

申请号：US17591928

申请日：2022-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-soo YU ,  Shinhaeng KANG ,  Yuhwan RO

IPC: G06F13/16 ,  G06F9/30

Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

公开(公告)号：US20210200696A1

公开(公告)日：2021-07-01

申请号：US16869853

申请日：2020-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Sukhan LEE

IPC: G06F13/16 ,  G06F13/40

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

公开(公告)号：US20200210296A1

公开(公告)日：2020-07-02

申请号：US16456094

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Joonho SONG ,  Seungwon LEE

IPC: G06F11/20 ,  G06F12/0815 ,  G11C29/38 ,  H01L25/065 ,  H01L25/18

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

公开(公告)号：US20200174749A1

公开(公告)日：2020-06-04

申请号：US16691033

申请日：2019-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Seongil O

IPC: G06F7/48 ,  G06F13/16 ,  G11C7/10

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.