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公开(公告)号:US20230138813A1
公开(公告)日:2023-05-04
申请号:US17978507
申请日:2022-11-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sunkyoung SEO , Chajea JO , Yeongseon KIM , Juhyeon KIM , Hyoeun KIM
IPC: H01L23/00 , H01L23/48 , H01L25/065
Abstract: A first semiconductor chip includes a first semiconductor substrate, a first wiring structure arranged on the first semiconductor substrate, a plurality of through electrodes penetrating through at least a portion of the first semiconductor substrate, and a plurality of first bonding pads respectively connected to the plurality of through electrodes. A second semiconductor chip is stacked on the first semiconductor chip and includes a second semiconductor substrate, a second wiring structure arranged on the second semiconductor substrate, and a second bonding pad connected to each of the plurality of first bonding pads and arranged on the active surface of the second semiconductor substrate. Each first bonding pad has a top surface that is in direct contact with the second bonding pad and a bottom surface that is in direct contact with one through electrode.
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公开(公告)号:US20220262689A1
公开(公告)日:2022-08-18
申请号:US17733411
申请日:2022-04-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyoeun KIM , Yonghoe CHO , Sunkyoung SEO , Seunghoon YEON , Sanguk HAN
Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
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公开(公告)号:US20210183816A1
公开(公告)日:2021-06-17
申请号:US16936882
申请日:2020-07-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joonho JUN , Un-Byoung KANG , Sunkyoung SEO , Jongho LEE , Young Kun JEE
IPC: H01L25/065 , H01L23/00
Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
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