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公开(公告)号：US20230207532A1
公开(公告)日：2023-06-29
申请号：US18176058
申请日：2023-02-28
发明人： Joonho JUN , Un-Byoung Kang , Sunkyoung Seo , Jongho Lee , Young Kun Jee
IPC分类号： H01L25/065 , H01L23/00
CPC分类号： H01L25/0657 , H01L24/14 , H01L24/06 , H01L2224/06181 , H01L2224/1451 , H01L2224/06515 , H01L2224/0401 , H01L2225/06513
摘要： A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
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公开(公告)号：US20210183816A1
公开(公告)日：2021-06-17
申请号：US16936882
申请日：2020-07-23
发明人： Joonho JUN , Un-Byoung KANG , Sunkyoung SEO , Jongho LEE , Young Kun JEE
IPC分类号： H01L25/065 , H01L23/00
摘要： A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
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公开(公告)号：US20230420336A1
公开(公告)日：2023-12-28
申请号：US18085859
申请日：2022-12-21
发明人： Joonho JUN , Sangsick PARK , Chungsun LEE , Hyoungjoo LEE
IPC分类号： H01L23/42 , H01L23/498 , H01L23/31 , H01L23/00 , H01L21/56
CPC分类号： H01L23/42 , H01L23/49833 , H01L23/49816 , H01L23/3157 , H01L24/16 , H01L24/81 , H01L21/56 , H01L2224/16227 , H01L2224/81
摘要： A fan-out type semiconductor package is provided and may include: a package substrate; an interposer on an upper surface of the package substrate, the interposer including upper pads and lower pads electrically connected with the upper pads; conductive bumps between the package substrate and the lower pads of the interposer and electrically connecting the package substrate with the interposer; a semiconductor chip on a central portion of an upper surface of the interposer and electrically connected with the upper pads of the interposer; a molding member on an edge portion of the upper surface of the interposer, the molding member including an upper surface coplanar with an upper surface of the semiconductor chip; and a metal pillar structure vertically extending from the upper surface of the molding member to a lower surface of the interposer and configured to individually make contact with the lower pads of the interposer.
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公开(公告)号：US20220130802A1
公开(公告)日：2022-04-28
申请号：US17571796
申请日：2022-01-10
发明人： Joonho JUN , Un-Byoung KANG , Sunkyoung SEO , Jongho LEE , Young Kun JEE
IPC分类号： H01L25/065 , H01L23/00
摘要： A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
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