公开(公告)号：US11302396B2

公开(公告)日：2022-04-12

申请号：US16862167

申请日：2020-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Youngsun Min ,  Daeseok Byeon ,  Kyunghwa Yun

IPC: G11C8/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C16/10 ,  H01L27/1157

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

公开(公告)号：US11237955B2

公开(公告)日：2022-02-01

申请号：US17007501

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Taehong Kwon ,  Chanho Kim ,  Taeyun Lee

IPC: G11C16/34 ,  G06F12/02 ,  G06F12/123 ,  G06F12/0811 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4074 ,  G06F12/14

Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.