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公开(公告)号：US09369115B2
公开(公告)日：2016-06-14
申请号：US14637670
申请日：2015-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Vivek Venkata Kalluru , Youngsun Min , Hichoon Lee
CPC classification number: H03K5/023 , G11C5/145 , G11C13/0038 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/30 , G11C16/32 , Y10T29/49169
Abstract: A voltage doubler includes first to fourth transistors, a first capacitor connected between a first node and a first clock terminal configured to receive a first clock signal. A second capacitor is connected between a second node and a second clock terminal configured to receive an inverted first clock signal. A first gate control unit is configured to control the first and second transistors using the first clock signal and the inverted first clock signal, and a second gate control unit is configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal. A load capacitor is connected between the output terminal and a ground terminal.
Abstract translation: 电压倍增器包括第一至第四晶体管，连接在第一节点和被配置为接收第一时钟信号的第一时钟端子之间的第一电容器。 第二电容器连接在第二节点和被配置为接收反相第一时钟信号的第二时钟端子之间。 第一栅极控制单元被配置为使用第一时钟信号和反相的第一时钟信号来控制第一和第二晶体管，并且第二栅极控制单元被配置为使用第二时钟信号和反相的第二时钟信号来控制第三和第四晶体管 时钟信号。 负载电容连接在输出端子和接地端子之间。
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公开(公告)号：US11289467B2
公开(公告)日：2022-03-29
申请号：US16944711
申请日：2020-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taehong Kwon , Youngsun Min , Daeseok Byeon , Kyunghwa Yun
IPC: G11C5/06 , H01L25/18 , H01L23/00 , H01L25/065 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/30
Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.
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3.发明申请公开(公告)号：US20140204676A1
公开(公告)日：2014-07-24
申请号：US14077769
申请日：2013-11-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taehyun Kim , Youngsun Min , Bilal Ahmad Janjua , Jeongdon Ihm
IPC: G11C16/30
CPC classification number: G11C16/30 , G11C16/0483 , G11C16/12
Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.
Abstract translation: 非易失性存储器件的高电压开关包括耗尽型NMOS晶体管，其配置为响应于高电压开关的输出信号而切换第二驱动电压; 至少一个反相器，被配置为将高压开关的输入信号的电压转换为第一驱动电压或接地电压，其中从外部装置接收第一和第二驱动电压; 以及PMOS晶体管，被配置为响应于所述至少一个反相器的输出，将提供给所述PMOS晶体管的第一端子的所述第二驱动电压从所述耗尽型NMOS晶体管传送到所述PMOS晶体管的第二端子作为所述输出信号， 其中所述至少一个反相器的输出被传送到所述PMOS晶体管的栅极端子。
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公开(公告)号：US09076511B2
公开(公告)日：2015-07-07
申请号：US14087444
申请日：2013-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taehyun Kim , Youngcho Kim , Youngsun Min , Sungwhan Seo
Abstract: A nonvolatile memory device includes a memory cell array; and a high voltage generator arranged to generate a high voltage to be supplied to the memory cell array. The high voltage generator includes a pump unit block having a plurality of pump units supplied with an external voltage and at least one of the pumps is engaged in pumping the external voltage to a higher, output, voltage, at a steady clock rate. The number of pumps engaged in pumping is increased until a predetermined period has elapsed. The rate at which the number of pumps is increased depends upon the value of the external voltage.
Abstract translation: 非易失性存储器件包括存储单元阵列; 以及高电压发生器，其布置成产生要提供给存储单元阵列的高电压。 高压发生器包括具有供给外部电压的多个泵单元的泵单元块，并且至少一个泵接合以以稳定的时钟速率将外部电压泵送到更高的输出电压。 泵送的泵的数量增加直到经过了预定时间。 泵数量增加的速率取决于外部电压的值。
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Patent Agency Ranking
公开(公告)号：US20140233337A1
公开(公告)日：2014-08-21
申请号：US14087444
申请日：2013-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taehyun Kim , Youngcho Kim , Youngsun Min , Sungwhan Seo
IPC: G11C5/14
Abstract: A nonvolatile memory device includes a memory cell array; and a high voltage generator arranged to generate a high voltage to be supplied to the memory cell array. The high voltage generator includes a pump unit block having a plurality of pump units supplied with an external voltage and at least one of the pumps is engaged in pumping the external voltage to a higher, output, voltage, at a steady clock rate. The number of pumps engaged in pumping is increased until a predetermined period has elapsed. The rate at which the number of pumps is increased depends upon the value of the external voltage.
Abstract translation: 非易失性存储器件包括存储单元阵列; 以及高电压发生器，其布置成产生要提供给存储单元阵列的高电压。 高压发生器包括具有供给外部电压的多个泵单元的泵单元块，并且至少一个泵接合以以稳定的时钟速率将外部电压泵送到更高的输出电压。 泵送的泵的数量增加直到经过了预定时间。 泵数量增加的速率取决于外部电压的值。
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公开(公告)号：US11302396B2
公开(公告)日：2022-04-12
申请号：US16862167
申请日：2020-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taehong Kwon , Youngsun Min , Daeseok Byeon , Kyunghwa Yun
Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.
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公开(公告)号：US11139021B2
公开(公告)日：2021-10-05
申请号：US16809016
申请日：2020-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seheon Baek , Youngsun Min
IPC: G11C7/00 , G11C11/4091 , G11C11/4094 , G11C11/4093 , G11C5/02 , G11C7/22 , G11C7/10 , G11C11/4074
Abstract: A memory device includes a first page buffer supplying a first bias voltage to a selected bitline in a bitline precharge phase; and a second page buffer supplying a second bias voltage to an unselected bitline, adjacent to the selected bitline, in the bitline precharge phase, wherein the first page buffer includes a first bitline precharge circuit supplying the first bias voltage to the selected bitline, the second page buffer includes a second bitline precharge circuit supplying the second bias voltage to the unselected bitline, wherein the second page buffer floats the unselected bitline in a sensing phase for detecting data of a selected memory cell connected to the selected to bitline.
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8.发明授权High voltage switch, nonvolatile memory device comprising same, and related method of operation 有权高压开关，包含该高压开关的非易失性存储器件及其相关操作方法公开(公告)号：US09349457B2
公开(公告)日：2016-05-24
申请号：US14455344
申请日：2014-08-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taehyun Kim , Youngsun Min
CPC classification number: G11C16/08 , G11C16/12 , G11C16/3418 , H03K17/165
Abstract: A high voltage switch operates in response to a first drive voltage and a second drive voltage higher than the first drive voltage. The high voltage switch includes a PMOS transistor transmitting the second drive voltage to an output terminal according to a voltage applied to its gate, a first depletion mode transistor providing the second drive voltage to the PMOS transistor according to an output signal fed back from the output terminal, a second depletion mode transistor receiving the second drive voltage through one end and providing a switching voltage to another end according to a switching control signal, and a level shifter providing the switching voltage to a gate of the PMOS transistor according to an enable signal and a reverse enable signal.
Abstract translation: 高电压开关响应于高于第一驱动电压的第一驱动电压和第二驱动电压而工作。 高压开关包括PMOS晶体管，其根据施加到其栅极的电压将第二驱动电压传输到输出端，第一耗尽模式晶体管，根据从输出端反馈的输出信号，向PMOS晶体管提供第二驱动电压 端子，第二耗尽型晶体管，通过一端接收第二驱动电压，并根据开关控制信号向另一端提供开关电压;以及电平移位器，根据使能信号向PMOS晶体管的栅极提供开关电压 和反向使能信号。
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公开(公告)号：US09147489B2
公开(公告)日：2015-09-29
申请号：US14077769
申请日：2013-11-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taehyun Kim , Youngsun Min , Bilal Ahmad Janjua , Jeongdon Ihm
CPC classification number: G11C16/30 , G11C16/0483 , G11C16/12
Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.
Abstract translation: 非易失性存储器件的高电压开关包括耗尽型NMOS晶体管，其配置为响应于高电压开关的输出信号而切换第二驱动电压; 至少一个反相器，被配置为将高压开关的输入信号的电压转换为第一驱动电压或接地电压，其中从外部装置接收第一和第二驱动电压; 以及PMOS晶体管，被配置为响应于所述至少一个反相器的输出，将提供给所述PMOS晶体管的第一端子的所述第二驱动电压从所述耗尽型NMOS晶体管传送到所述PMOS晶体管的第二端子作为所述输出信号， 其中所述至少一个反相器的输出被传送到所述PMOS晶体管的栅极端子。
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